ZL40219LDG1 Microchip

ZL40219 Precision 1:8 LVDS Fanout Buffer with On-Chip Input Termination Data Sheet November 2012 Features Ordering Information ZL40219LDG1 32 Pin QFN Trays Inputs/Outputs ZL40219LDF1 32 Pin QFN Tape and Reel Accepts differential or single-ended input Matte Tin LVPECL, LVDS, CML, HCSL, LVCMOS Package size: 5 x 5 mm o o On-chip input termination and biasing for AC -40 C to +85 C coupled inputs Eight precision LVDS outputs Applications Operating frequency up to 750 MHz General purpose clock distribution Power Low jitter clock trees Options for 2.5 V or 3.3 V power supply Logic translation Current consumption of 112 mA Clock and data signal restoration On-chip Low Drop Out (LDO) Regulator for superior Wired communications: OTN, SONET/SDH, GE, power supply rejection 10 GE, FC and 10G FC Performance Wireless communications Ultra low additive jitter of 135 fs RMS High performance micro-processor clock distribution out0 p out0 n out1 p out1 n out2 p out2 n ctrl Termination and Bias vt out3 p out3 n clk p Buffer clk n out4 p out4 n out5 p out5 n out6 p out6 n out7 p out7 n Figure 1 - Functional Block Diagram 1 Microsemi Corporation Copyright 2012, Microsemi Corporation. All Rights Reserved.ZL40219 Data Sheet Table of Contents Features . 1 Inputs/Outputs . 1 Power 1 Performance . 1 Applications . 1 1.0 Package Description 4 2.0 Pin Description . 5 3.0 Functional Description 6 3.1 Clock Inputs . 6 3.2 Clock Outputs 11 3.3 Device Additive Jitter . 14 3.4 Power Supply 15 3.4.1 Sensitivity to power supply noise . 15 3.4.2 Power supply filtering 15 3.4.3 PCB layout considerations 15 4.0 AC and DC Electrical Characteristics . 16 5.0 Performance Characterization . 18 6.0 Typical Behavior 19 7.0 Package Characteristics 20 8.0 Mechanical Drawing . 21 2 Microsemi Corporation