512Mb: x32 Automotive Mobile LPDDR2 SDRAM 1 Features Automotive Mobile LPDDR2 SDRAM EDB5432BEBH, EDB5432BEPA 1 Options Marking Features V : 1.2V B DD2 Ultra low-voltage core and I/O power supplies Density/Page Size V = 1.141.30V DD2 512Mb/2KB - single die 54 V /V = 1.141.30V DDCA DDQ Organization V = 1.701.95V DD1 x32 32 Clock frequency range FBGA green package 53310 MHz (data rate range: 106620 Mb/s/pin) 134-ball VFBGA BH Four-bit prefetch DDR architecture (10mm x 11.5mm) Four internal banks for concurrent operation 168-ball WFBGA PA Multiplexed, double data rate, command/address (12mm x 12mm) inputs commands entered on every CK edge Timing cycle time Bidirectional/differential data strobe per byte of 1.875ns RL = 8 -1D data (DQS/DQS ) Special options Programmable READ and WRITE latencies (RL/WL) Standard None Programmable burst lengths: 4, 8, or 16 Automotive certified A On-chip temperature sensor to control self refresh (Package-level burn-in) rate Operating temperature range 2 Partial-array self refresh (PASR) From 40C to +85C IT Deep power-down mode (DPD) From 40C to +105C AT Selectable output drive strength (DS) 3 From 40C to +125C UT Clock stop capability Revision :E RoHS-compliant, green packaging 1. All items related to 8-bank in this data Notes: sheet are not available. For example per- Table 1: Key Timing Parameters bank refresh option is not supported. 2. When T > 105C, self-refresh mode is not C Speed Clock Rate Data Rate available. t t Grade (MHz) (Mb/s/pin) RL WL RCD/ RP 3. UT option use based on automotive usage -1D 533 1066 8 4 Typical model. Please contact Micron sales repre- sentative if you have questions. 09005aef86573be0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 u97m auto lpddr2 ait aat aut.pdf - Rev. G 07/17 EN 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x32 Automotive Mobile LPDDR2 SDRAM 1 Features Table 2: Single Channel S4 Configuration Addressing Architecture 16 Meg x 32 Die configuration 4 Meg x 32 x 4 banks Row addressing 8K (A 12:0 ) Column addressing 512 (A 8:0 ) Number of die 1 Die per rank 1 1 Ranks per channel 1 Note: 1. A channel is a complete LPDRAM interface, including command/address and data pins. Figure 1: 512Mb LPDDR2 Part Numbering E D B 54 32 B E BH -1D A AT -F Embedded Memory Environment Code -F = Lead free (RoHS compliant and Halogen free) Type D = Packaged device Operating Temperature IT = 40C to +85C Product Family AT = 40C to +105C B = DDR2 Mobile RAM UT = 40C to +125C Density/Page size Special Options 54 = 512Mb/2KB A = Automotive grade Organization Speed (package only) 32 = x32 -1D = 1066 Mbps Power Supply and Interface Package B = V = 1.8V V = V = V = 1.2V DD1 DD2 DDCA DDQ BH = 134-ball VFBGA (10mm x 11.5mm) S4B device HSUL PA = 168-ball WFBGA (12mm x 12mm) Revision = E FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. Table 3: Package Codes and Descriptions Package Die per Solder Ball Code Ball Count Ranks Channels Size (mm) Package Composition BH 134 1 1 10 x 11.5 x 1.0, 0.65 pitch SDP SAC302 PA 168 1 1 12 x 12 x 0.8, 0.5 pitch SDP SAC302 Notes: 1. SDP = Single-die package. 2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu). 09005aef86573be0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 u97m auto lpddr2 ait aat aut.pdf - Rev. G 07/17 EN 2015 Micron Technology, Inc. All rights reserved.