Preliminary
168-Ball LPDDR2 SDRAM Addendum
Features
Data Sheet Addendum: LPDDR2 SDRAM
EDB8132B4PB-8D-F-R, EDB8132B4PB-8D-F-D
Options
Features
V /V /V : 1.8V/1.2V/1.2V
DD1 DD2 DDQ
This addendum documents features of the Micron
Array configuration
4Gb Mobile Low-Power DDR2 SDRAM (LPDDR2) de-
256 Meg x 32 (DDP)
vice.
Packaging
12mm x 12mm, 168-ball PoP FBGA package
This addendum does not provide detailed device in-
Operating temperature range
formation. The standard density-specific device data
From 30C to +85C
sheet provides a complete description of device func-
tionality, operating modes, and specifications unless
specified herein.
Information provided here is in addition to or super-
sedes information in the device data sheet.
Ultra-low-voltage core and I/O power supplies
Frequency range
400 MHz (data rate: 800 Mb/s/pin)
4n prefetch DDR architecture
8 internal banks for concurrent operation
Multiplexed, double data rate, command/address
inputs; commands entered on each CK_t/CK_c
edge
Bidirectional/differential data strobe per byte of
data (DQS_t/DQS_c)
Programmable READ and WRITE latencies (RL/WL)
Burst length: 4, 8, and 16
Per-bank refresh for concurrent operation
Auto temperature-compensated self refresh
(ATCSR) by built-in temperature sensor
Partial-array self refresh (PASR)
Deep power-down mode (DPD)
Selectable output drive strength (DS)
Clock-stop capability
Lead-free (RoHS-compliant) and halogen-free
packaging
Table 1: Configuration Addressing Single-Channel Package
Architecture 256 Meg x 32
Density per package 8Gb
Die per package 2
Ranks per channel 1
Die per rank 2
Configuration 32 Meg x 16 x 8 banks x 2
PDF: 09005aef85a1f01d Micron Technology, Inc. reserves the right to change products or specifications without notice.
1
168b_lpddr2_sdram_addendum.pdf Rev. B 7/14 EN 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Microns production data sheet specifications.Preliminary
168-Ball LPDDR2 SDRAM Addendum
Features
Table 1: Configuration Addressing Single-Channel Package (Continued)
Architecture 256 Meg x 32
Row addressing 16K A[13:0]
Column addressing 2K A[10:0]
Table 2: Key Timing Parameters
Speed Clock Rate Data Rate WRITE READ
Grade (MHz) (Mb/s/pin) Latency Latency
8D 400 800 3 6
Table 3: Part Number Description
Part Total Package Ball
Number Density Configuration Ranks Channels Size Pitch
EDB8132B4PB-8D-F-R, 8Gb 256 Meg x 32 1 1 12mm x 12mm 0.50mm
EDB8132B4PB-8D-F-D (0.80mm MAX height)
Figure 1: Marketing Part Number Chart
-
E D B 81 32 B 4 PB - 8D - F D
Micron Technology Packing Media
D = Dry Pack (Tray)
R = Tape and Reel
Type
D = Packaged device Environment Code
F = Lead-free (RoHS-compliant)
Product Family and halogen-free
B = Mobile LPDDR2 SDRAM
Speed
Density/Chip Select 8D = 800 Mb/s
81 = 8Gb/2-CS
Package
PB = BGA for PoP
Organization
Revision
32 = x32
Power Supply Interface
B = V = 1.8V, V = V = 1.2V,
DD1 DD2 DDQ
S4B device, HSUL
1. The characters highlighted in gray indicate the physical part marking found on the device.
Note:
PDF: 09005aef85a1f01d Micron Technology, Inc. reserves the right to change products or specifications without notice.
2
168b_lpddr2_sdram_addendum.pdf Rev. B 7/14 EN 2014 Micron Technology, Inc. All rights reserved.