2Gb: x8, x16 Automotive DDR3L SDRAM
Description
1.35V Automotive DDR3L SDRAM
MT41K256M8 32 Meg x 8 x 8 banks
MT41K128M16 16 Meg x 16 x 8 banks
Output driver calibration
Description
2
AEC-Q100
The 1.35V DDR3L SDRAM device is a low-voltage ver-
PPAP submission
sion of the 1.5V DDR3 SDRAM device. Refer to the
8D response time
DDR3 (1.5V) SDRAM data sheet specifications when
running in 1.5V compatible mode.
Options Marking
Configuration
Features
256 Meg x 8 256M8
V = V = 1.35V (1.2831.45V)
DD DDQ
128 Meg x 16 128M16
Backward-compatible to V = V = 1.5V 0.075V
DD DDQ
FBGA package (Pb-free)
Differential bidirectional data strobe
78-ball FBGA (8mm x 10.5mm) DA
8n-bit prefetch architecture
x8
Differential clock inputs (CK, CK#)
96-ball FBGA (8mm x 14mm) JT
8 internal banks
x16
Nominal and dynamic on-die termination (ODT)
Timing cycle time
for data, strobe, and mask signals
1.07ns @ CL = 13 (DDR3-1866) -107
Programmable CAS (READ) latency (CL)
1.25ns @ CL = 11 (DDR3-1600) -125
Programmable posted CAS additive latency (AL)
1.5ns @ CL = 9 (DDR3-1333) -15E
Programmable CAS (WRITE) latency (CWL)
1.875ns @ CL = 7 (DDR3-1066) -187E
Fixed burst length (BL) of 8 and burst chop (BC) of 4
Product certification
(via the mode register set [MRS])
Automotive A
Selectable BC4 or BL8 on-the-fly (OTF)
Operating temperature
Self refresh mode
Industrial (40C T +95C) IT
C
Refresh maximum interval time at T temperature
C
Automotive (40C T +105C) AT
C
range
3
Ultra-high (40C T +125C) UT
C
64ms at 40C to +85C
Revision :K
32ms at +85C to +105C
16ms at +105C to +115C
1. Not all options listed can be combined to
Notes:
8ms at +115C to +125C
define an offered product. Use the part cat-
Self refresh temperature (SRT)
alog search on
Automatic self refresh (ASR)
2Gb: x8, x16 Automotive DDR3L SDRAM
Description
Table 1: Key Timing Parameters (Continued)
t t t t
Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns)
1
-15E 1333 9-9-9 13.5 13.5 13.5
-187E 1066 7-7-7 13.1 13.1 13.1
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
3. Backward compatible to 1600, CL = 11 (-125).
Table 2: Addressing
Parameter 256 Meg x 8 128 Meg x 16
Configuration 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks
Refresh count 8K 8K
Row address 32K A[14:0] 16K A[13:0]
Bank address 8 BA[2:0] 8 BA[2:0]
Column address 1K A[9:0] 1K A[9:0]
Figure 1: DDR3L Part Numbers
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1. Not all options listed can be combined to define an offered product. Use the part catalog search on
Note: