2Gb: x4, x8, x16 Automotive DDR3L SDRAM Addendum Description 1.35V Automotive DDR3L SDRAM Data Sheet Addendum MT41K512M4 64 Meg x 4 x 8 banks MT41K256M8 32 Meg x 8 x 8 banks MT41K128M16 16 Meg x 16 x 8 banks Automatic self refresh (ASR) Description Write leveling The 1.35V DDR3L SDRAM device is a low-voltage ver- Multipurpose register sion of the 1.5V DDR3 SDRAM device. Unless stated Output driver calibration otherwise, the DDR3L SDRAM device meets the func- AEC-Q100 tional and timing specifications listed in the equiva- PPAP submission lent density standard or automotive DDR3 SDRAM 8D response time data sheet located on www.micron.com. Options Marking Features Configuration V = V = 1.35V (1.2831.45V) DD DDQ 512 Meg x 4 512M4 Backward-compatible to V = V = 1.5V 0.075V DD DDQ 256 Meg x 8 256M8 Differential bidirectional data strobe 128 Meg x 16 128M16 8n-bit prefetch architecture FBGA package (Pb-free) x4, x8 Differential clock inputs (CK, CK ) 78-ball (8mm x 10.5mm) Rev. K DA 8 internal banks FBGA package (Pb-free) x16 Nominal and dynamic on-die termination (ODT) 96-ball FBGA (8mm x 14mm) JT for data, strobe, and mask signals Rev. K Programmable CAS (READ) latency (CL) Timing cycle time Programmable posted CAS additive latency (AL) 1.25ns CL = 11 (DDR3-1600) -125 Programmable CAS (WRITE) latency (CWL) 1.5ns CL = 9 (DDR3-1333) -15E Fixed burst length (BL) of 8 and burst chop (BC) of 4 1.875ns CL = 7 (DDR3-1066) -187E (via the mode register set MRS ) Special Options Selectable BC4 or BL8 on-the-fly (OTF) Product Longevity Program (PLP) X Self refresh mode Automotive certification A T of 0C to +95C C Operating temperature 64ms, 8192-cycle refresh at 0C to +85C Industrial (40C T +95C) IT C 32ms at +85C to +95C Automotive (40C T +105C) AT C Self refresh temperature (SRT) Revision :K Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 1, 2 -125 1600 11-11-11 13.75 13.75 13.75 1 -15E 1333 9-9-9 13.5 13.5 13.5 -187E 1066 7-7-7 13.1 13.1 13.1 1. Backward compatible to 1066, CL = 7 (-187E). Notes: 2. Backward compatible to 1333, CL = 9 (-15E). PDF: 09005aef8599fe25 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 2Gb auto ddr3l sdram addendum.pdf - Rev. A 03/14 EN 2014 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.2Gb: x4, x8, x16 Automotive DDR3L SDRAM Addendum Description Table 2: Addressing Parameter 512 Meg x 4 256 Meg x 8 128 Meg x 16 Configuration 64 Meg x 4 x 8 banks 32 Meg x 8 x 8 banks 16 Meg x 16 x 8 banks Refresh count 8K 8K 8K Row address 32K A 14:0 32K A 14:0 16K A 13:0 Bank address 8 BA 2:0 8 BA 2:0 8 BA 2:0 Column address 2K A 11, 9:0 1K A 9:0 1K A 9:0 Figure 1: DDR3L Part Numbers Example Part Number: MT41K256M8DA-125:K - : MT41K Configuration Package Timing Revision :K Revision Configuration 512 Meg x 4 512M4 Operating Temperature 256 Meg x 8 256M8 Industrial IT 128 Meg x 16 128M16 Automotive AT Package Rev Mark Special Options* 78-ball 8mm x 10.5mm FBGA K DA Automotive A 96-ball 8mm x 14mm FBGA K JT Product Longevity Program (PLP) X *Multiple processing codes are separated by a space and are listed Timing in hierarchical order. t CK = 1.25ns, CL = 11 -125 t CK = 1.5ns, CL = 9 -15E t -187E CK = 1.87ns, CL = 7 Note: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on