4Gb: x4, x8, x16 DDR4 SDRAM Features DDR4 SDRAM MT40A1G4 MT40A512M8 MT40A256M16 1 Options Marking Features Configuration V = V = 1.2V 60mV DD DDQ 1 Gig x 4 1G4 V = 2.5V, 125mV/+250mV PP 512 Meg x 8 512M8 On-die, internal, adjustable V generation 2 REFDQ 256 Meg x 16 256M16 1.2V pseudo open-drain I/O FBGA package (Pb-free) x4, x8 T maximum up to 95C C 78-ball (9mm x 11.5mm) Rev. A HX 64ms, 8192-cycle refresh up to 85C 78-ball (9mm x 10.5mm) Rev. B RH 32ms, 8192-cycle refresh at >85C to 95C FBGA package (Pb-free) x16 16 internal banks (x4, x8): 4 groups of 4 banks each 96-ball (9mm x 14mm) Rev. A HA 8 internal banks (x16): 2 groups of 4 banks each 96-ball (9mm x 14mm) Rev. B GE 8n-bit prefetch architecture Timing cycle time Programmable data strobe preambles 0.625ns CL = 22 (DDR4-3200) -062E Data strobe preamble training 0.682ns CL = 20 (DDR4-2933) -068E Command/Address latency (CAL) 0.682ns CL = 21 (DDR4-2933) -068 Multipurpose register READ and WRITE capability 0.750ns CL = 18 (DDR4-2666) -075E Write and read leveling 0.750ns CL = 19 (DDR4-2666) -075 Self refresh mode 0.833ns CL = 16 (DDR4-2400) -083E Low-power auto self refresh (LPASR) 0.833ns CL = 17 (DDR4-2400) -083 Temperature controlled refresh (TCR) 0.937ns CL = 15 (DDR4-2133) -093E Fine granularity refresh 0.937ns CL = 16 (DDR4-2133) -093 Self refresh abort 1.071ns CL = 13 (DDR4-1866) -107E Maximum power saving Operating temperature Output driver calibration Commercial (0 T 95C) None C Nominal, park, and dynamic on-die termination Industrial (40 T 95C) IT C (ODT) Revision :A Data bus inversion (DBI) for data bus :B Command/Address (CA) parity 1. Not all options listed can be combined to Notes: Databus write cyclic redundancy check (CRC) define an offered product. Use the part Per-DRAM addressability catalog search on 4Gb: x4, x8, x16 DDR4 SDRAM Features Table 1: Key Timing Parameters t t t t Speed Grade Data Rate (MT/s) Target RCD- RP-CL RCD (ns) RP (ns) CL (ns) 6 -062E 3200 22-22-22 13.75 13.75 13.75 5 -068E 2933 20-20-20 13.64 13.64 13.64 5 -068 2933 21-21-21 14.32 14.32 14.32 4 -075E 2666 18-18-18 13.5 13.5 13.5 4 -075 2666 19-19-19 14.25 14.25 14.25 3 -083E 2400 16-16-16 13.32 13.32 13.32 3 -083 2400 17-17-17 14.16 14.16 14.16 2 -093E 2133 15-15-15 14.06 14.06 14.06 2 -093 2133 16-16-16 15 15 15 1 -107E 1866 13-13-13 13.92 13.92 13.92 Notes: 1. Backward compatible to 1600, CL = 11. 2. Backward compatible to 1600, CL = 11 and 1866, CL = 13. 3. Backward compatible to 1600, CL = 11 1866, CL = 13 and 2133, CL = 15. 4. Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 and 2400, CL = 17. 5. Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 and 2666, CL = 19. Speed offering may have restricted availability. 6. Backward compatible to 1600, CL = 11 1866, CL = 13 2133, CL = 15 2400, CL = 17 2666, CL = 19 and 2933, CL = 20 and CL = 21. Speed offering may have restricted availability. Table 2: Addressing Parameter 1024 Meg x 4 512 Meg x 8 256 Meg x 16 Number of bank groups 4 4 2 Bank group address BG 1:0 BG 1:0 BG0 Bank count per group 4 4 4 Bank address in bank group BA 1:0 BA 1:0 BA 1:0 Row addressing 64K (A 15:0 ) 32K (A 14:0 ) 32K (A 14:0 ) Column addressing 1K (A 9:0 ) 1K (A 9:0 ) 1K (A 9:0 ) 1 2 Page size 512B / 1KB 1KB 2KB 1. Page size is per bank, calculated as follows: Notes: COLBITS Page size = 2 ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. 2. Die revision dependant. 09005aef84af6dd0 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 4gb ddr4 dram.pdf - Rev. J 7/17 EN 2014 Micron Technology, Inc. All rights reserved.