MT46H16M32LFCM-6:B TR Micron

512Mb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H32M16LF 8 Meg x 16 x 4 Banks MT46H16M32LF 4 Meg x 32 x 4 Banks Options Marking Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H 1 1.2V I/O option V = 1.141.30V DDQ 1.8V/1.2V HC Bidirectional data strobe per byte of data (DQS) Configuration 32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16 Internal, pipelined double data rate (DDR)architec- 16 Meg x 32 (4 Meg x 32 x 4 banks) 16M32 ture two data accesses per clock cycle Row-size option Differential clock inputs (CK and CK ) JEDEC-standard option LF Commands entered on each positive CK edge 1 Reduced page-size option LG DQS edge-aligned with data for READs center- Plastic green package aligned with data for WRITEs 2 60-ball VFBGA (8mm x 9mm) BF 3 4 internal banks for concurrent operation 90-ball VFBGA (10mm x 13mm) CM 3 Data masks (DM) for masking write dataone mask 90-ball VFBGA (9mm x 13mm) CX per byte Timing cycle time 5ns CL = 3 -5 Programmable burst lengths (BL): 2, 4, 8, or 16 5.4ns CL = 3 -54 Concurrent auto precharge option is supported 6ns CL = 3 -6 Auto refresh and self refresh modes 7.5ns CL = 3 -75 1.8V LVCMOS-compatible inputs Power On-chip temp sensor to control self refresh rate Standard I /I None DD2 DD6 1 Partial-array self refresh (PASR) Low-power I /I L DD2 DD6 Operating temperature range Deep power-down (DPD) Commercial (0 to +70C) None Status read register (SRR) Industrial (40C to +85C) IT Selectable output drive strength (DS) Design revision :B Clock stop capability 1. Contact factory for availability. Notes: 64ms refresh 2. Only available for x16 configuration. 3. Only available for x32 configuration. Table 1: Key Timing Parameters (CL = 3) Speed Grade Clock Rate Access Time -5 200 MHz 5.0ns -54 185 MHz 5.0ns -6 166 MHz 5.0ns -75 133 MHz 6.0ns PDF: 09005aef82d5d305 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 512mb ddr mobile sdram t47m.pdf Rev. I 12/09 EN 2004 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.512Mb: x16, x32 Mobile LPDDR SDRAM Features Table 2: Configuration Addressing Reduced Page Size Architecture 32 Meg x 16 16 Meg x 32 16 Meg x 32 Configuration 8 Meg x 16 x 4 banks 4 Meg x 32 x 4 banks 4 Meg x 32 x 4 banks Refresh count 8K 8K 8K Row addressing A 12:0 A 12:0 A 13:0 Column addressing A 9:0 A 8:0 A 7:0 Figure 1: 512Mb Mobile LPDDR Part Numbering MT 46 H 32M16 LF BF -6 IT :C Micron Technology Design Revision :C = Third generation Product Family 46 = Mobile LPDDR Operating Temperature Blank = Commercial (0C to +70C) Operating Voltage IT = Industrial (40C to +85C) H = 1.8/1.8V AT = Automotive (40C to +105C) Configuration Power 32 Meg x 16 Blank = Standard I /I DD2 DD6 16 Meg x 32 Cycle Time (CL = 3) t Addressing -5 = 5ns CK t LF = JEDEC-standard -54 = 5.4ns CK t LG = Reduced page size -6 = 6ns CK t -75 = 7.5ns CK Package Codes BF = 60-ball (8mm x 9mm) VFBGA, green B5 = 90-ball (8mm x 13mm) VFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef82d5d305 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 512mb ddr mobile sdram t47m.pdf Rev. I 12/09 EN 2004 Micron Technology, Inc. All rights reserved.