MT46H8M16LFBF-6 IT:K TR Micron

128Mb: x16, x32 Mobile LPDDR SDRAM Features Mobile Low-Power DDR SDRAM MT46H8M16LF 2 Meg x 16 x 4 Banks MT46H4M32LF 1 Meg x 32 x 4 Banks Options Marking Features V /V DD DDQ V /V = 1.701.95V DD DDQ 1.8V/1.8V H Bidirectional data strobe per byte of data (DQS) Configuration Internal, pipelined double data rate (DDR) architec- 8 Meg x 16 (2 Meg x 16 x 4 8M16 ture two data accesses per clock cycle banks) 4 Meg x 32 (1 Meg x 32 x 4 4M32 Differential clock inputs (CK and CK ) banks) Commands entered on each positive CK edge Row size option DQS edge-aligned with data for READs center- JEDEC-standard option LF aligned with data for WRITEs Plasticgree package 4 internal banks for concurrent operation 1 60-ball VFBGA (8mm x 9mm) BF 2 Data masks (DM) for masking write data one mask 90-ball VFBGA (8mm x 13mm) B5 per byte Timing cycle time Programmable burst lengths (BL): 2, 4, 8, or 16 5ns CL = 3 (200 MHz) -5 5.4ns CL = 3 (185 MHz) -54 Concurrent auto precharge option is supported 6ns CL = 3 (166 MHz) -6 Auto refresh and self refresh modes 7.5ns CL = 3 (133 MHz) -75 1.8V LVCMOS-compatible inputs Operating temperature range Temperature-compensated self refresh (TCSR) Commercial (0 to +70C) None Partial-array self refresh (PASR) Industrial (40C to +85C) IT Deep power-down (DPD) Design revision :K Status read register (SRR) 1. Only available for x16 configuration. Notes: Selectable output drive strength (DS) 2. Only available for x32 configuration. Clock stop capability 64ms refresh Table 1: Key Timing Parameters (CL = 3) Speed Grade Clock Rate Access Time -5 200 MHz 5.0ns -54 185 MHz 5.0ns -6 166 MHz 5.0ns -75 133 MHz 6.0ns PDF: 09005aef8331b3e9 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1 128mb mobile ddr sdram t35m.pdf - Rev. F 03/10 EN 2007 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice.128Mb: x16, x32 Mobile LPDDR SDRAM Features Table 2: Configuration Addressing Architecture 8 Meg x 16 4 Meg x 32 Configuration 2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks Refresh count 4K 4K Row addressing 4K A 11:0 4K A 11:0 Column addressing 512 A 8:0 256 A 7:0 Figure 1: 128Mb Mobile LPDDR Part Numbering MT 46 H 8M16 LF BF -6 IT :K Micron Technology Design Revision :K Product Family 46 = Mobile LPDDR Operating Temperature Blank = Commercial (0C to +70C) Operating Voltage IT = Industrial (40C to +85C) H = 1.8/1.8V Cycle Time (CL = 3) t -5 = 5ns CK t Configuration -54 = 5.4ns CK t 8 Meg x 16 -6 = 6ns CK t 4 Meg x 32 -75 = 7.5ns CK Addressing Package Codes LF = JEDEC-standard addressing BF = 8mm x 9mm VFBGA, green B5 = 8mm x 13mm VFBGA, green FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Microns FBGA part marking decoder is available at www.micron.com/decoder. PDF: 09005aef8331b3e9 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2 128mb mobile ddr sdram t35m.pdf - Rev. F 03/10 EN 2007 Micron Technology, Inc. All rights reserved.