TRC103 Product Overview 863-960 MHz TRC103 is a single chip, multi-channel, low power UHF transceiver. It is RF Transceiver designed for low cost, high volume, two-way short range wireless applica- tions in the 863-870, 902-928 and 950-960 MHz frequency bands. The TRC103 is FCC & ETSI certifiable. All critical RF and base-band functions are integrated in the TRC103, minimizing external component count and sim- plifying and speeding design-ins. A microcontroller, RF SAW filter, 12.8 MHz crystal and a few passive components are all that is needed to create a com- plete, robust radio function. The TRC103 incorporates a set of low-power states to reduce overall current consumption and extend battery life. The small size and low power consumption of the TRC103 make it ideal for a wide variety of short range radio applications. The TRC103 complies with Directive 2002/95/EC (RoHS). Pb Key Features Modulation: FSK or OOK with frequency hop- Integrated RSSI ping and DTS spread spectrum capability Integrated crystal oscillator Frequency ranges: 863-870, 902-928 and Host processor interrupt pins 950-960 MHz Programmable data rate High sensitivity: -112 dBm in circuit External wake-up event inputs High data rate: up to 200 kb/s Integrated packet CRC error detection Low receiver current: 3.3 mA typical Integrated DC-balanced data scrambling Low sleep current: 0.1 A typical Integrated Manchester encoding/decoding Up to +11 dBm in-circuit transmit power Interrupt signal mapping function Operating supply voltage: 2.1 to 3.6 V Support for multiple channels Programmable preamble Four power-saving modes Programmable packet start pattern Low external component count Integrated RF, PLL, IF and base-band circuitry Small 32-pin QFN plastic package Integrated data & clock recovery Standard 13 inch reel, 3K pieces Programmable RF output power Applications PLL lock output Transmit/receive FIFO size programmable up Active RFID tags to 64 bytes Automated meter reading Continuous, Buffered and Packet data modes Home & industrial automation Packet address recognition Security systems Packet handling features: Two-way remote keyless entry Fixed or variable packet length Automobile immobilizers Packet filtering Sports performance monitoring Packet formatting Wireless toys Standard SPI interface Medical equipment TTL/CMOS compatible I/O pins Low power two-way telemetry systems Programmable clock output frequency Wireless mesh sensor networks Low cost 12.8 MHz crystal reference Wireless modules www.RFM.com E-mail: info rfm.com Technical support +1.800.704.6079 Page 1 of 65 2009-2010 by RF Monolithics, Inc. TRC103 - 11/29/12 Table of Contents 1.0 Pin Configuration ..................................................................................................................................... 4 1.1 Pin Description .................................................................................................................................. 4 2.0 Functional Description ............................................................................................................................. 5 2.1 RF Port .............................................................................................................................................. 7 2.2 Transmitter ........................................................................................................................................ 7 2.3 Receiver ............................................................................................................................................ 8 2.4 Crystal Oscillator ............................................................................................................................... 9 2.5 Frequency Synthesizer ................................................................................................................... 10 2.6 PLL Loop Filter ................................................................................................................................ 10 3.0 Operating Modes ................................................................................................................................... 11 3.1 Receiving in Continuous Mode ....................................................................................................... 12 3.2 Continuous Mode Data and Clock Recovery .................................................................................. 13 3.3 Continuous Mode Start Pattern Recognition .................................................................................. 14 3.4 RSSI ................................................................................................................................................ 14 3.5 Receiving in Buffered Data Mode ................................................................................................... 15 3.6 Transmitting in Continuous or Buffered Data Modes ...................................................................... 17 3.7 IRQ0 and IRQ1 Mapping................................................................................................................. 17 3.8 Buffered Clock Output ..................................................................................................................... 19 3.9 Packet Data Modes ......................................................................................................................... 19 3.9.1 Fixed Length Packet Mode .................................................................................................... 19 3.9.2 Variable Length Packet Mode ............................................................................................... 20 3.9.3 Extended Variable Length Packet Mode ............................................................................... 20 3.9.4 Packet Payload Processing in Transmit and Receive ........................................................... 22 3.9.5 Packet Filtering ...................................................................................................................... 23 3.9.6 Cyclic Redundancy Check ..................................................................................................... 23 3.9.7 Manchester Encoding ............................................................................................................ 24 3.9.8 DC-Balanced Scrambling ...................................................................................................... 24 3.10 SPI Configuration Interface ........................................................................................................... 25 3.11 SPI Data FIFO Interface ............................................................................................................... 27 4.0 Configuration Register Memory Map ..................................................................................................... 28 4.1 Main Configuration Registers (MCFG) ............................................................................................ 29 4.2 Interrupt Configuration Registers (IRQCFG)................................................................................... 32 4.3 Receiver Configuration Registers (RXCFG) ................................................................................... 34 4.4 Start Pattern Configuration Registers (SYNCFG) ........................................................................... 37 4.5 Transmitter Configuration Registers (TXCFG)................................................................................ 37 4.6 Oscillator Configuration Register (OSCFG) .................................................................................... 38 4.7 Packet Handler Configuration Registers (PKTCFG) ....................................................................... 38 4.8 Page Configuration Register (PGCFG) ........................................................................................... 39 5.0 Electrical Characteristics ....................................................................................................................... 40 5.1 DC Electrical Characteristics .......................................................................................................... 40 5.2 AC Electrical Characteristics ........................................................................................................... 41 6.0 TRC103 Design-in Steps ....................................................................................................................... 43 6.1 Determining Frequency Specific Hardware Component Values .................................................... 43 6.1.1 SAW Filters and Related Component Values ....................................................................... 43 6.1.2 Voltage Controlled Oscillator Component Values ................................................................. 43 6.2 Determining Configuration Values for FSK Modulation .................................................................. 44 6.2.1 Bit Rate Related FSK Configuration Values .......................................................................... 44 6.2.2 Determining Transmitter Power Configuration Values .......................................................... 46 www.RFM.com E-mail: info rfm.com Technical support +1.800.704.6079 Page 2 of 65 2009-2010 by RF Monolithics, Inc. TRC103 - 11/29/12