STA8088FG STMicroelectronics

STA8088FG Fully Integrated GPS/Galileo/Glonass/QZSS Receiver with embedded RF and in-package Flash Data brief preliminary data Features rd STMicroelectronics 3 generation positioning receiver with 32 Tracking channels and 2 fast acquisition channels compatible with GPS, Galileo and Glonass systems VFQFPN56 Embedded RF Front-End with separate (7x7x0.85mm) GPS/Galieo/QZSS and Glonass IF outputs Embedded low noise amplifier -162 dBm indoor sensitivity (tracking mode) Fast TTFF < 1 s in Hot start and 35 s in Cold Package: Start VFQFPN56 (7 x 7 x 0.85 mm) 0.4 mm High performance ARM946 MCU (up to pitch 208 MHz) Ambient temperature range: -40/+85C 256 Kbyte embedded SRAM In-Package SQI Flash Memory (16 Mbits) Description Real Time Clock (RTC) circuit STA8088FG is a single die standalone positioning 32-bit Watch-dog timer receiver IC working on multiple constellations 3 UARTs (GPS/Galileo/Glonass/QZSS). 2 1 I C master/slave interface The minimum BOM make STA8088FG the ideal 1 Synchronous Serial Port (SSP, Motorola-SPI solution for low-cost and small footprint products supported) or 1 External SQI Flash interface such handheld computers, cameras, data USB2.0 dual-role full speed (12 MHz) with loggers, and sports accessories. integrated physical layer transceiver The device is offered with a complete GNSS 2 Controller Area Network (CAN) firmware which performs all GNSS operations including tracking, acquisition, navigation and 2 channels ADC (10 bits) data output with no need of external memories 3 Embedded 1.8 V voltage regulators I/O level selectable 1.8 V or 3.3 V Operating Condition: V : 1.2 V 10% DD12 V : 1.8 V 5% DD18/RF18 V 1.62 V to 3.6 V LPVR V : 1.8 V 5% 3.3 V 10% ddIO September 2013 Doc ID 022731 Rev 3 1/17 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to www.st.com 1 change without notice. For further information contact your local STMicroelectronics sales office.Contents STA8088FG Contents 1 Overview 5 2 Pin description . 6 2.1 Block diagram . 6 2.2 VFQFPN56 pin configuration 7 2.3 Power supply pins . 8 2.4 Main function pins . 9 2.5 Test/emulated dedicated pins . 10 2.6 RF front-end pins . 10 2.7 Port 0 pins 10 2.8 Port 1 pins 11 3 Package and packing information . 13 3.1 ECOPACK packages . 13 3.2 VFQFPN56 7 x 7 x 0.85 mm package information 13 4 Ordering information . 15 5 Revision history . 16 2/17 Doc ID 022731 Rev 3