74ABT32 Quad 2-input OR gate Rev. 4 9 October 2020 Product data sheet 1. General description The 74ABT32 is a quad 2-input OR gate. This device is fully specified for partial power down applications using I . The I circuitry disables the output, preventing the potentially damaging OFF OFF backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 4.5 V to 5.5 V BiCMOS high speed and output drive Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ABT32D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ABT32PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mmNexperia 74ABT32 Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B A 12 12 4A 1 4Y 11 11 Y 13 4B 13 B mna242 mna243 mna241 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74ABT32 74ABT32 1A 1 14 V CC 1B 2 13 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 1Y 3 12 4A 2A 4 11 4Y 2A 4 11 4Y 2B 5 10 3B 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y GND 7 8 3Y aaa-024198 aaa-024199 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A, 2A, 3A, 4A 1, 4, 9, 12 data input 1B, 2B, 3B, 4B 2, 5, 10, 13 data input 1Y, 2Y, 3Y, 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74ABT32 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 4 9 October 2020 2 / 10