74AHC00BQ Nexperia

74AHC00 74AHCT00 Quad 2-input NAND gate Rev. 04 28 April 2008 Product data sheet 1. General description The 74AHC00 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. JESD7-A. The 74AHC00 74AHCT00 provides the quad 2-input NAND function. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger actions n Inputs accept voltages higher than V CC n Input levels: u For 74AHC00: CMOS level u For 74AHCT00: TTL level n ESD protection: u HBM EIA/JESD22-A114E exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V u CDM EIA/JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC00 74AHC00D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHC00PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHC00BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm74AHC00 74AHCT00 NXP Semiconductors Quad 2-input NAND gate Table 1. Ordering information continued Type number Package Temperature range Name Description Version 74AHCT00 74AHCT00D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT00PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT00BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals body 2.5 3 0.85 mm 4. Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 9 3A 3Y 8 & 8 10 3B 10 A 12 4A 12 4Y 11 Y 13 4B & 11 13 B mna212 mna246 mna211 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning terminal 1 index area 2 13 1B 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 2A 4 00 11 4Y 1Y 3 12 4A 2A 4 00 11 4Y 2B 5 (1) 10 3B GND 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y 001aac939 001aac938 Transparent top view (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 4. Pin conguration SO14 and TSSOP14 Fig 5. Pin conguration DHVQFN14 74AHC AHCT00 4 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 28 April 2008 2 of 14 7 1 GND 1A 3Y 8 14 V CC