74AHC3GU04DP,125 Nexperia

74AHC3GU04 Triple unbuffered inverter Rev. 6 27 February 2019 Product data sheet 1. General description The 74AHC3GU04 is a high-speed Si-gate CMOS device. This device provides three inverter gates with unbuffered outputs. 2. Features and benefits Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000 V Low power dissipation Balanced propagation delays Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC3GU04DP -40 C to +125 C TSSOP8 plastic thin shrink small outline package SOT505-2 8 leads body width 3 mm lead length 0.5 mm 74AHC3GU04DC -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 4. Marking Table 2. Marking codes Type number Marking code 1 74AHC3GU04DP AU4 74AHC3GU04DC AU4 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code.Nexperia 74AHC3GU04 Triple unbuffered inverter 5. Functional diagram 1 1 7 1 1A 1Y 7 1 3 5 3 2A 2Y 5 1 6 3A 3Y 2 6 2 A Y mna720 mna721 mna045 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 6. Pinning information 6.1. Pinning 74AHC3GU04 1A 1 8 V CC 3Y 2 7 1Y 2A 3 6 3A GND 4 5 2Y 001aaj517 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1A, 2A, 3A 1, 3, 6 data input GND 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 data output V 8 supply voltage CC 7. Functional description Table 4. Function table H = HIGH voltage level L = LOW voltage level Input Output A Y L H H L 74AHC3GU04 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 6 27 February 2019 2 / 13