74AHC595D,112 Nexperia

74AHC595 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches Rev. 6 26 May 2020 Product data sheet 1. General description The 74AHC595 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register. Data in the storage register appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595 and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as translators in mixed voltage environments. 2. Features and benefits Wide supply voltage range from 2.0 V to 5.5 V Balanced propagation delays All inputs have Schmitt-trigger action Overvoltage tolerant inputs to 5.5 V High noise immunity CMOS low power dissipation Input levels: The 74AHC595 operates with CMOS input levels The 74AHCT595 operates with TTL input levels ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74AHC595 74AHCT595 8-bit serial-in/serial-out or parallel-out shift register with output latches 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC595D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74AHCT595D 74AHC595PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AHCT595PW 74AHC595BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals 74AHCT595BQ body 2.5 3.5 0.85 mm 5. Functional diagram 14 DS 11 SHCP 8-STAGE SHIFT REGISTER 10 MR Q7S 9 12 STCP 8-BIT STORAGE REGISTER 13 OE 3-STATE OUTPUTS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 15 1 2 3 4 5 6 7 mna554 Fig. 1. Functional diagram 13 EN3 12 C2 11 12 10 SHCP STCP SRG8 R 11 9 C1/ Q7S 15 Q0 14 15 1D 2D 3 1 Q1 1 2 Q2 2 14 3 Q3 DS 3 4 Q4 4 5 Q5 5 6 Q6 6 7 Q7 7 MR OE 9 10 13 mna552 mna553 Fig. 2. Logic symbol Fig. 3. IEC logic symbol 74AHC AHCT595 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 6 26 May 2020 2 / 19