74AHCT126BQ Nexperia

74AHC126 74AHCT126 Quad buffer/line driver 3-state Rev. 04 12 August 2009 Product data sheet 1. General description The 74AHC126 74AHCT126 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specied in compliance with JEDEC standard No. 7-A. The 74AHC126 74AHCT126 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A LOW-level at pin nOE causes the outputs to assume a high-impedance OFF-state. The 74AHC126 74AHCT126 is identical to the 74AHC125 74AHCT125 but has active HIGH output enable inputs. 2. Features n Balanced propagation delays n All inputs have Schmitt-trigger action n Inputs accept voltages higher than V CC n Input levels: u For 74AHC126: CMOS level u For 74AHCT126: TTL level n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C74AHC126 74AHCT126 NXP Semiconductors Quad buffer/line driver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC126D - 40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74AHCT126D 74AHC126PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74AHCT126PW 74AHC126BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package no leads 14 terminals 74AHCT126BQ body 2.5 3 0.85 mm 4. Functional diagram 2 1A 1Y 3 1OE 1 5 2A 2Y 6 4 2OE 3A 3Y 8 9 10 3OE 12 4A 4Y 11 4OE 13 mna235 Fig 1. Functional diagram 2 1 3 1 EN1 5 6 4 9 8 10 nY nA 12 11 13 nOE mna234 mna236 Fig 2. Logic symbol Fig 3. IEC logic symbol 74AHC AHCT126 4 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 12 August 2009 2 of 15