74AHCT2G08GD,125 Nexperia

74AHC2G08; 74AHCT2G08 Dual 2-input AND gate Rev. 5 27 November 2013 Product data sheet 1. General description The 74AHC2G08; 74AHCT2G08 is a high-speed Si-gate CMOS device. The 74AHC2G08; 74AHCT2G08 provides two 2-input AND gates. 2. Features and benefits Symmetrical output impedance High noise immunity ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101C exceeds 1000 V Low power dissipation Balanced propagation delays Multiple package options Specified from 40 Cto+80 C and from 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC2G08DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; body SOT505-2 width 3 mm; lead length 0.5 mm 74AHCT2G08DP 74AHC2G08DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm 74AHCT2G08DC 74AHC2G08GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; SOT996-2 8 terminals; body 3 2 0.5 mm 74AHCT2G08GD74AHC2G08; 74AHCT2G08 Nexperia Dual 2-input AND gate 4. Marking Table 2. Marking [1] Type number Marking code 74AHC2G08DP A08 74AHCT2G08DP C08 74AHC2G08DC A08 74AHCT2G08DC C08 74AHC2G08GD A08 74AHCT2G08GD C08 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 1 & 7 2 1 1A 1Y 7 2 1B 5 2A 5 & 2Y 3 3 6 2B 6 mna725 mna724 Fig 1. Logic symbol. Fig 2. IEC logic symbol. A Y B mna221 Fig 3. Logic diagram (one gate). 74AHC_AHCT2G08 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 5 27 November 2013 2 of 15