74AHCT2G125DC-Q10H Nexperia

74AHC2G125-Q100 74AHCT2G125-Q100 Dual buffer/line driver 3-state Rev. 2 2 January 2019 Product data sheet 1. General description The 74AHC2G125-Q100 and 74AHCT2G125-Q100 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line driver with 3-state output. The output enable input (nOE) controls the 3-state output. A HIGH at nOE causes the output to assume a high-impedance OFF-state. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Symmetrical output impedance High noise immunity Low power dissipation Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC2G125DP-Q100 -40 C to +125 C TSSOP8 plastic thin shrink small outline package SOT505-2 8 leads body width 3 mm lead length 0.5 mm 74AHCT2G125DP-Q100 74AHC2G125DC-Q100 -40 C to +125 C VSSOP8 plastic very thin shrink small outline package SOT765-1 8 leads body width 2.3 mm 74AHCT2G125DC-Q100Nexperia 74AHC2G125-Q100 74AHCT2G125-Q100 Dual buffer/line driver 3-state 4. Marking Table 2. Marking codes Type number Marking 1 74AHC2G125DP-Q100 A25 74AHCT2G125DP-Q100 C25 74AHC2G125DC-Q100 A25 74AHCT2G125DC-Q100 C25 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 2 1A 1Y 6 2 1 1OE 6 1 1 EN1 5 2A 2Y 3 nA nY 5 3 2 7 2OE 7 EN2 nOE mce185 mce186 mna227 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 6. Pinning information 6.1. Pinning 74AHC2G125-Q100 74AHCT2G125-Q100 1OE 1 8 V CC 1A 2 7 2OE 2Y 3 6 1Y GND 4 5 2A aaa-010127 Fig. 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) 6.2. Pin description Table 3. Pin description Symbol Pin Description 1OE, 2OE 1, 7 output enable input (active LOW) 1A, 2A 2, 5 data input GND 4 ground (0 V) 1Y, 2Y 6, 3 data output V 8 supply voltage CC 74AHC AHCT2G125 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 2 2 January 2019 2 / 12