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This literature is subject to all applicable copyright laws and is not for resale in any manner.74LCX125 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs December 2013 74LCX125 Low Voltage Quad Buffer with 5V Tolerant Inputs and Outputs Features General Description 5V tolerant inputs and outputs The LCX125 contains four independent non-inverting buffers with 3-STATE outputs. The inputs tolerate volt- 2.3V3.6V V specifications provided CC ages up to 7V allowing the interface of 5V systems to 3V 6.0ns t max. (V = 3.3V), 10A I max. PD CC CC systems. Power down high impedance inputs and outputs (1) The 74LCX125 is fabricated with an advanced CMOS Supports live insertion/withdrawal technology to achieve high speed operation while main- 24mA output drive (V = 3.0V) CC taining CMOS low power dissipation. Implements proprietary noise/EMI reduction circuitry Latch-up performance exceeds JEDEC 78 conditions ESD performance: Human body model > 2000V Machine model > 100V Leadless DQFN package Note: 1. To ensure the high-impedance state during power up or down, OE should be tied to V through a pull-up CC resistor: the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Information Package Order Number Number Package Description 74LCX125M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 74LCX125SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide (2) 74LCX125BQX MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 3.0mm 74LCX125MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Note: 2. DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. 1995 Fairchild Semiconductor Corporation www.fairchildsemi.com 74LCX125 Rev. 1.7.1