74ALVC00D-Q100J Nexperia

74ALVC00-Q100 Quad 2-input NAND gate Rev. 3 30 April 2021 Product data sheet 1. General description The 74ALVC00-Q100 is a quad 2-input NAND gate. Schmitt trigger action on all inputs makes the device tolerant of slow rise and fall times. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 3) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 3) Specified from -40 C to +85 C Wide supply voltage range from 1.65 V to 3.6 V 3.6 V tolerant inputs/outputs CMOS low power consumption Direct interface with TTL levels (2.7 V to 3.6 V) Power-down mode Latch-up performance exceeds 250 mA Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVC00D-Q100 -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74ALVC00PW-Q100 -40 C to +85 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74ALVC00BQ-Q100 -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74ALVC00-Q100 Quad 2-input NAND gate 4. Functional diagram 1 3 & 1 1A 2 1Y 3 2 1B 4 4 2A 6 & 2Y 6 5 5 2B 9 9 3A 3Y 8 8 & 10 3B 10 A 12 4A 12 4Y 11 Y 11 13 4B & 13 B mna212 mna246 mna211 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning 74ALVC00 terminal 1 index area 1B 2 13 4B 74ALVC00 1Y 3 12 4A 2A 4 11 4Y 1 14 1A V CC 5 10 2B (1) 3B GND 2 13 1B 4B 2Y 6 9 3A 3 12 1Y 4A 4 11 2A 4Y aaa-032330 5 10 2B 3B 6 9 2Y 3A Transparent top view 7 8 GND 3Y (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case aaa-032329 soldered, the solder land should remain floating or connected to GND Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74ALVC00 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 3 30 April 2021 2 / 12 7 1 GND 1A 3Y 8 14 V CC