74ALVC74BQ Nexperia

INTEGRATED CIRCUITS DATA SHEET 74ALVC74 Dual D-type flip-flop with set and reset positive-edge trigger Product specication 2003 May 26 Supersedes data of 2003 Jan 24Philips Semiconductors Product specication Dual D-type ip-op with set and reset 74ALVC74 positive-edge trigger FEATURES DESCRIPTION Wide supply voltage range from 1.65 to 3.6 V The 74ALVC74 is a dual positive-edge triggered, D-type flip-flop with individual data (D), clock (CP), set (SD) and Complies with JEDEC standard: reset (RD) inputs and complementary Q and Q outputs. JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) The set and reset are asynchronous active LOW inputs JESD8B/JESD36 (2.7 to 3.6 V). and operate independently of the clock input. Information on the data input is transferred to the Q output on the 3.6 V tolerant inputs/outputs LOW-to-HIGH transition of the clock pulse. The D inputs CMOS low power consumption must be stable one set-up time prior to the LOW-to-HIGH Direct interface with TTL levels (2.7 to 3.6 V) clock transition for predictable operation. Power-down mode Schmitt-trigger action in the clock input makes the circuit Latch-up performance exceeds 250 mA highly tolerant to slower clock rise and fall times. ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V T =25 C. amb SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t /t propagation delay nCP to nQ, nQV = 1.8 V C = 30 pF R =1k 3.7 ns PHL PLH CC L L V = 2.5 V C = 30 pF R = 500 2.6 ns CC L L V = 2.7 V C = 50 pF R = 500 2.8 ns CC L L V = 3.3 V C = 50 pF R = 500 2.7 ns CC L L t /t propagation delay nSD, nRD to nQ, nQV = 1.8 V C = 30 pF R =1k 3.5 ns PHL PLH CC L L V = 2.5 V C = 30 pF R = 500 2.5 ns CC L L V = 2.7 V C = 50 pF R = 500 3.1 ns CC L L V = 3.3 V C = 50 pF R = 500 2.3 ns CC L L f maximum clock frequency 425 MHz max C input capacitance 3.5 pF I C power dissipation capacitance per buffer V = 3.3 V notes 1 and 2 35 pF PD CC Notes 1. C is used to determine the dynamic power dissipation (P in W). PD D 2 2 P =C V f N+ (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in Volts CC N = total load switching outputs 2 (C V f ) = sum of the outputs. L CC o 2. The condition is V = GND to V . I CC 2003 May 26 2