74ALVCH16500 18-bit universal bus transceiver 3-state Rev. 3 11 December 2017 Product data sheet 1 General description The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A data is stored in the latch/flip-flop on the HIGH-to-LOW transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW). To ensure the high impedance state during power up or power down, OEBA should be tied to V through a pullup resistor and OEAB should be tied to GND CC through a pulldown resistor the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2 Features and benefits CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels (2.7 V to 3.6 V) Bus hold on data inputs Output drive capability 50 transmission lines at 85 C Current drive 24 mA at 3.0 V Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 VNexperia 74ALVCH16500 18-bit universal bus transceiver 3-state 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH16500DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mm 4 Functional diagram 1 OEAB EN1 55 CPBA 2C3 2 LEAB C3 G2 27 OEBA EN4 30 A0 B0 CPBA 5C6 3 54 28 A1 B1 LEBA C6 5 52 G5 A2 B2 6 51 A3 B3 3 54 8 49 A0 B0 3D 1 1 A4 B4 9 48 4 1 6D A5 B5 5 52 10 47 A1 B1 A6 B6 6 51 12 45 A2 B2 A7 B7 8 49 13 44 A3 B3 A8 B8 9 48 14 43 A4 B4 A9 B9 10 47 15 42 A5 B5 A10 B10 12 45 16 41 A6 B6 A11 B11 13 44 17 40 A7 B7 A12 B12 14 43 19 38 A8 B8 A13 B13 15 42 20 37 A9 B9 A14 B14 16 41 21 36 A10 B10 A15 B15 17 40 23 34 A11 B11 A16 B16 19 38 24 33 A12 B12 A17 B17 20 37 26 31 A13 B13 21 36 A14 B14 OEAB OEBA 23 34 1 27 A15 B15 LEAB LEBA 24 33 2 28 A16 B16 CPAB CPBA 26 31 55 30 A17 B17 aaa-027848 aaa-027849 Figure 1.Logic symbol Figure 2.IEC logic symbol V CC data input to internal circuit 001aal733 Figure 3.Bus hold circuit 74ALVCH16500 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 3 11 December 2017 2 / 17