74ALVCH16952DGGS Nexperia

74ALVCH16952 16-bit registered transceiver 3-state Rev. 3 9 January 2018 Product data sheet 1 General description The 74ALVCH16952 consists of two sections, each containing a dual octal non-inverting registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Data applied to the inputs is entered and stored on the rising edge of the clock (nCPAB and nCPBA) provided that the clock enable (nCEAB and nCEBA) is LOW. The data is then present at the output buffers, but is only accessible when the output enable input (nOEAB and nOEBA) is LOW. Data flow from A inputs to B outputs is the same as for B inputs to A outputs. 2 Features and benefits CMOS low-power consumption Multibyte flow-through pinout architecture Low inductance, multiple center power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Output drive capability 50 transmission lines at 85 C Complies with JEDEC standard JESD8-B 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH16952DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mmNexperia 74ALVCH16952 16-bit registered transceiver 3-state 4 Functional diagram 5 52 15 42 1A0 1B0 2A0 2B0 6 51 16 41 1A1 1B1 2A1 2B1 8 49 17 40 1A2 1B2 2A2 2B2 9 48 19 38 1A3 1B3 2A3 2B3 10 47 20 37 1A4 1B4 2A4 2B4 12 45 22 36 1A5 1B5 2A5 2B5 13 44 23 34 1A6 1B6 2A6 2B6 14 43 24 33 1A7 1B7 2A7 2B7 56 1 3 54 2 55 29 28 26 31 27 30 1OEBA 2OEBA 1OEAB 2OEAB 1CEAB 2CEAB 1CEBA 2CEBA 1CPAB 2CPAB 1CPBA 2CPBA 001aae552 Figure 1.Logic symbol 56 1EN3 1OEBA 54 1CEBA G1 55 1CPBA 1C5 1 1OEAB EN4 3 1CEAB G2 2 2C6 1CPAB 29 EN9 2OEBA 31 2CEBA G7 30 7C11 2CPBA 28 2OEAB EN10 26 2CEAB G8 27 8C12 2CPAB 5 52 1A0 1B0 3 5D 6D 4 6 51 1A1 1B1 8 49 1A2 1B2 9 48 1A3 1B3 10 47 1A4 1B4 12 45 1A5 1B5 13 44 1A6 1B6 14 43 1A7 1B7 15 42 V CC 2A0 2B0 9 11D 12D 10 16 41 2A1 2B1 17 40 2A2 2B2 19 38 2A3 2B3 data input to internal circuit 20 37 2A4 2B4 21 36 2A5 2B5 23 34 2A6 2B6 24 33 2A7 2B7 001aae550 001aad245 Figure 2.IEC logic symbol Figure 3.Bus hold circuit 74ALVCH16952 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 9 January 2018 2 / 14