74AUP1G00GW-Q100H Nexperia

74AUP1G00-Q100 Low-power 2-input NAND gate Rev. 2 13 January 2022 Product data sheet 1. General description The 74AUP1G00-Q100 is a single 2-input NAND gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is fully CC specified for partial power down applications using I . The I circuitry disables the output, OFF OFF preventing the damaging backflow current through the device when it is powered down. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 Vto 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V MIL-STD-883, method 3015 Class 3A exceeds 5000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Overvoltage tolerant inputs to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFFNexperia 74AUP1G00-Q100 Low-power 2-input NAND gate 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G00GW-Q100 -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G00GW-Q100 pA 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram B 1 1 B & Y 4 4 Y 2 A 2 A mna097 mna098 mna099 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G00 B 1 5 V CC A 2 GND 3 4 Y 001aaf016 Fig. 4. Pin configuration SOT353-1 (TSSOP5) 74AUP1G00 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2022. All rights reserved Product data sheet Rev. 2 13 January 2022 2 / 14