74AUP1G175GF,132 Nexperia

74AUP1G175 Low-power D-type flip-flop with reset positive-edge trigger Rev. 6 2 April 2021 Product data sheet 1. General description The 74AUP1G175 provides a low-power, low-voltage positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic CC power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP1G175 Low-power D-type flip-flop with reset positive-edge trigger 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G175GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1G175GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G175GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G175GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G175GW aT 74AUP1G175GM aT 74AUP1G175GN aT 74AUP1G175GS aT 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 6 MR 3 1 D CP 4 FF 3 4 Q D Q 1 CP 6 MR 001aaa468 001aaa469 Fig. 1. Logic symbol Fig. 2. IEC logic symbol CP C Q C C C C C C C D C C MR 001aaa466 Fig. 3. Logic diagram 74AUP1G175 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 2 April 2021 2 / 21