74AUP1G386GW,125 Nexperia

74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate Rev. 7 8 December 2020 Product data sheet 1. General description The 74AUP1G386 is a single 3-input EXCLUSIVE-OR gate. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. This device is CC fully specified for partial power down applications using I . The I circuitry disables the output, OFF OFF preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V CMOS low power dissipation High noise immunity Overvoltage tolerant inputs to 3.6 V Low static power consumption I = 0.9 A (maximum) CC Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 100 mA per JESD 78 Class II Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G386GW -40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1G386GM -40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1G386GN -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1G386GS -40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mmNexperia 74AUP1G386 Low-power 3-input EXCLUSIVE-OR gate 4. Marking Table 2. Marking Type number Marking code 1 74AUP1G386GW aH 74AUP1G386GM aH 74AUP1G386GN aH 74AUP1G386GS aH 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram A 1 B Y 1 = 1 3 4 3 4 C 6 6 mnb143 mnb145 Fig. 1. Logic symbol Fig. 2. IEC logic symbol A B Y C mnb144 Fig. 3. Logic diagram 6. Pinning information 6.1. Pinning 74AUP1G386 74AUP1G386 74AUP1G386 A 1 6 C A 1 6 C 1 6 A C GND 2 5 V CC GND 2 5 V CC 2 5 GND V CC B 3 4 Y B 3 4 Y 001aad938 B 3 4 Y 001aad939 Transparent top view 001aad937 Transparent top view Fig. 6. Pin configuration SOT1115 Fig. 4. Pin configuration SOT363 Fig. 5. Pin configuration SOT886 and SOT1202 74AUP1G386 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 7 8 December 2020 2 / 16