74AUP1T02GWH Nexperia

74AUP1T02 Low-power 2-input NOR gate with voltage-level translator Rev. 1 28 November 2017 Product data sheet 1 General description The 74AUP1T02 provides the single 2-input NOR function. This device ensures a very low static and dynamic power consumption across the entire V range from CC 2.3 V to 3.6 V. The 74AUP1T02 is designed for logic-level translation applications with input switching levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single 2.5 V or 3.3 V supply voltage. The wide supply voltage range ensures normal operation as battery voltage drops from 3.6 V to 2.3 V. This device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across the entire V range. CC 2 Features and benefits Wide supply voltage range from 2.3 V to 3.6 V High noise immunity ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 1.5 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AUP1T02 Low-power 2-input NOR gate with voltage-level translator 3 Ordering information Table 1.Ordering information Type number Package Temperature Name Description Version range 74AUP1T02GW -40 C to +125 C TSSOP5 plastic thin shrink small outline package 5 leads SOT353-1 body width 1.25 mm 74AUP1T02GX -40 C to +125 C X2SON5 plastic thermal enhanced extremely thin small outline SOT1226 package no leads 5 terminals body 0.8 x 0.8 x 0.35 mm 4 Marking Table 2.Marking 1 Type number Marking code 74AUP1T02GW 5F 74AUP1T02GX 5F 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5 Functional diagram 1 B B 1 Y 4 1 4 Y 2 A 2 A aaa-027762 aaa-027763 aaa-027764 Figure 1.Logic symbol Figure 2.IEC logic symbol Figure 3.Logic diagram 6 Pinning information 6.1 Pinning 74AUP1T02 74AUP1T02 B 1 5 V CC B 1 5 V CC 3 GND A 2 A 2 4 Y GND 3 4 Y aaa-027766 aaa-027765 Transparent top view Figure 4.Pin configuration SOT353-1 Figure 5.Pin configuration SOT1226 (X2SON5) 74AUP1T02 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 1 28 November 2017 2 / 15