74AUP1T1326
Low-power dual supply buffer/line driver; 3-state
Rev. 01 20 January 2009 Product data sheet
1. General description
The 74AUP1T1326 is a high-performance, low-power, low-voltage, single-bit, dual supply
buffer/line driver with output enable circuitry.
The 74AUP1T1326 is designed for logic-level translation applications and combines the
functions of the 74AUP1G32 and 74AUP1G126. The buffer/line driver is controlled by two
output enable Schmitt trigger inputs (1OE and 2OE) through an OR-gate. The output
enable inputs accept standard input signals and are capable of transforming slowly
changing input signals into sharply dened, jitter-free output signals. The output of the
OR-gate is also available at output 1Y.
The output enable inputs (1OE and 2OE) switch at different points for positive and
negative-going signals. The difference between the positive voltage V and the negative
T+
voltage V is dened as the input hysteresis voltage V .
T- H
Both V and V can be supplied at any voltage between 1.1 V and 3.6 V making
CC(A) CC(B)
the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V,
1.8 V, 2.5 V and 3.3 V) with compatible input levels. Pins 1OE, 2OE and 1Y are referenced
to V and pins A and 2Y are referenced to V . A logic LOW on both output enable
CC(A) CC(B)
pins causes the output 2Y to assume a high-impedance OFF-state.
The device ensures low static and dynamic power consumption and is fully specied for
partial power down applications using I . The I circuitry disables the outputs,
OFF OFF
preventing any damaging backow current through the device when it is powered down.
2. Features
n Wide supply voltage range:
u V : 1.1 V to 3.6 V; V : 1.1 V to 3.6 V.
CC(A) CC(B)
n High noise immunity
n Complies with JEDEC standards:
u JESD8-7 (1.2 V to 1.95 V)
u JESD8-5 (1.8 V to 2.7 V)
u JESD8-B (2.7 V to 3.6 V)
n ESD protection:
u HBM JESD22-A114E Class 2A exceeds 2000 V
u MM JESD22-A115-A exceeds 200 V
u CDM JESD22-C101C exceeds 1000 V
n Low static power consumption; I = 0.9 A (maximum)
CC
n Latch-up performance exceeds 100 mA per JESD 78 Class II
n Inputs accept voltages up to 3.6 V74AUP1T1326
NXP Semiconductors
Low-power dual supply buffer/line driver; 3-state
n Low noise overshoot and undershoot < 10 % of V
CC
n I circuitry provides partial Power-down mode operation
OFF
n Multiple package options
n Specied from - 40 Cto+85 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP1T1326GT - 40 C to +85 C XSON8 plastic extremely thin small outline package; no leads; SOT833-1
8 terminals; body 1 x 1.95 x 0.5 mm
4. Marking
Table 2. Marking
Type number Marking code
74AUP1T1326GT p31
5. Functional diagram
5
1OE
R 7
pd
1Y
6
2OE
R
pd
V
CC(A)
2 8
A 2Y
V
CC(B)
001aaj293
R = Internal pull-down resistor.
pd
Fig 1. Logic symbol
74AUP1T1326_1 NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 01 20 January 2009 2 of 24