74AUP1T45GW Nexperia

74AUP1T45 Low-power dual supply translating transceiver 3-state Rev. 5 9 August 2012 Product data sheet 1. General description The 74AUP1T45 is a single bit transceiver featuring two data input-outputs (A and B), a direction control input (DIR) and dual supply pins (V and V ) which enable CC(A) CC(B) bidirectional level translation. Both V and V can be supplied at any voltage CC(A) CC(B) between 1.1 V and 3.6 V making the device suitable for interfacing between any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins A and DIR are referenced to V and pin B is referenced to V . A HIGH on DIR allows transmission from A to B CC(A) CC(B) and a LOW on DIR allows transmission from B to A. Schmitt trigger action on all inputs makes the circuit tolerant of slower input rise and fall times across the entire V and V ranges. The device ensures low static and CC(A) CC(B) dynamic power consumption and is fully specified for partial power-down applications using I . The I circuitry disables the output, preventing any damaging backflow OFF OFF current through the device when it is powered down. In suspend mode when either V CC(A) or V are at GND, both A and B are in the high-impedance OFF-state. CC(B) 2. Features and benefits Wide supply voltage range: V : 1.1 V to 3.6 V CC(A) V : 1.1 V to 3.6 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption I = 0.9 A (maximum) CC Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1T45 NXP Semiconductors Low-power dual supply translating transceiver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1T45GW 40 C to +125 C SC-88 plastic surface-mounted package 6 leads SOT363 74AUP1T45GM 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT886 6 terminals body 1 1.45 0.5 mm 74AUP1T45GF 40 C to +125 C XSON6 plastic extremely thin small outline package no leads SOT891 6 terminals body 1 1 0.5 mm 74AUP1T45GN 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1115 6 terminals body 0.9 1.0 0.35 mm 74AUP1T45GS 40 C to +125 C XSON6 extremely thin small outline package no leads SOT1202 6 terminals body 1.0 1.0 0.35 mm 4. Marking Table 2. Marking 1 Type number Marking code 74AUP1T45GW p5 74AUP1T45GM p5 74AUP1T45GF p5 74AUP1T45GN p5 74AUP1T45GS p5 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram 5 DIR DIR 3 A A 4 B B V V CC(A) CC(B) V V CC(A) CC(B) 001aae962 001aae963 Fig 1. Logic symbol Fig 2. Logic diagram 74AUP1T45 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 5 9 August 2012 2 of 36