74AVC16T245DGG Nexperia

74AVC16T245 16-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 6 9 September 2013 Product data sheet 1. General description The 74AVC16T245 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs.The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (V and V ) for voltage translation and four 8-bit CC(A) CC(B) input-output ports (nAn and nBn) each with its own output enable (nOE) and send/receive (nDIR) input for direction control. V and V can be independently supplied at any CC(A) CC(B) voltage between 0.8 V and 3.6 V making the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at CC(A) CC(B) GND level, both nAn and nBn are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101D exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation)74AVC16T245 NXP Semiconductors 16-bit dual supply translating transceiver 3-state 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC16T245DGG 40 Cto+125 C TSSOP48 plastic thin shrink small outline package 48 leads SOT362-1 body width 6.1 mm 1 74AVC16T245DGV 40 Cto+125 CTSSOP48 plastic thin shrink small outline package 48 leads SOT480-1 body width 4.4 mm lead pitch 0.4 mm 74AVC16T245EV 40 Cto+125 C VFBGA56 plastic very thin fine-pitch ball grid array package SOT702-1 56 balls body 4.5 7 0.65 mm 74AVC16T245BX 40 Cto+125 C HXQFN60 plastic compatible thermal enhanced extremely SOT1134-2 thin quad flat package no leads 60 terminals body 4 6 0.5 mm 1 Also known as TVSOP48. 4. Functional diagram 1DIR 2DIR 1OE 2OE 1A1 2A1 1B1 2B1 V V V V CC(A) CC(B) CC(A) CC(B) to other seven channels to other seven channels 001aak426 Fig 1. Logic diagram 74AVC16T245 All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 6 9 September 2013 2 of 28