74AVC1T1004 1-to-4 fan-out buffer Rev. 2 1 March 2021 Product data sheet 1. General description The 74AVC1T1004 is a translating 1-to-4 fan-out buffer suitable for use in clock distribution. It has dual supplies (V and V ) for voltage translation. It also has a data input (A), four data CC(A) CC(B) outputs (Yn) and an output enable input (OE). V and V can be independently supplied CC(A) CC(B) at any voltage between 0.8 V and 3.6 V. It makes the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The levels of A and OE are referenced to V , outputs Yn are referenced to V . This supply configuration CC(A) CC(B) ensures that the fanned out signals can be used in level shifting. A HIGH on OE causes all outputs to be pulled LOW via pull-down resistors, a LOW on OE disconnects the pull-down resistors and enables all outputs. Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time. The I circuitry disables the output, preventing any damaging backflow current through the OFF device when it is powered down. 2. Features and benefits Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV CDM JESD22-C101 exceeds 1 kV Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Specified from -40 C to +85 C and -40 C to +125 CNexperia 74AVC1T1004 1-to-4 fan-out buffer 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC1T1004DP -40 C to +125 C TSSOP10 plastic thin shrink small outline package 10 leads SOT552-1 body width 3 mm 4. Marking Table 2. Marking codes Type number Marking code 74AVC1T1004DP Bc 5. Functional diagram V V CC(A) CC(B) 2 9 A Y4 R pd 8 Y3 R pd 4 OE 7 Y2 R pd 6 Y1 R pd aaa-027814 Fig. 1. Logic symbol 74AVC1T1004 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 2 1 March 2021 2 / 18