74AVC16T245-Q100 16-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 2 14 January 2019 Product data sheet 1. General description The 74AVC16T245-Q100 is a 16-bit transceiver with bidirectional level voltage translation and 3-state outputs. The device can be used as two 8-bit transceivers or as a 16-bit transceiver. It has dual supplies (V and V ) for voltage translation and four 8-bit input-output ports CC(A) CC(B) (nAn and nBn). Each port has its own output enable (nOE) and send/receive (nDIR) input for direction control. V and V can be independently supplied with any voltage between 0.8 V CC(A) CC(B) and 3.6 V. This flexibility makes the device suitable for low voltage translation between any of the following voltages: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. A HIGH on nDIR selects transmission from nAn to nBn while a LOW on nDIR selects transmission from nBn to nAn. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both nAn and nBn CC(A) CC(B) are in the high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 class 3B exceeds 8000 V HBM JESD22-A114E class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFFNexperia 74AVC16T245-Q100 16-bit dual supply translating transceiver with configurable voltage translation 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC16T245DGV-Q100 -40 C to +125 C TSSOP48 1 plastic thin shrink small outline package SOT480-1 48 leads body width 4.4 mm lead pitch 0.4 mm 1 Also known as TVSOP48. 4. Functional diagram 1DIR 2DIR 1OE 2OE 1A1 2A1 1B1 2B1 V V V V CC(A) CC(B) CC(A) CC(B) to other seven channels to other seven channels 001aak426 Fig. 1. Logic diagram 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 V V CC(A) CC(B) 1OE 1DIR 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2B1 2B2 2B3 2B4 2B5 2B6 2B7 2B8 V V CC(A) CC(B) 2OE 2DIR 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 001aak425 Fig. 2. Logic symbol 74AVC16T245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 2 14 January 2019 2 / 20