74AVC2T245GU-Q100X Nexperia

74AVC2T245-Q100 2-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 1 14 June 2019 Product data sheet 1. General description The 74AVC2T245-Q100 is a 2-bit, dual supply transceiver that enables bidirectional level translation. The device can be used as two 1-bit transceivers or as a 2-bit transceiver. It features two 2-bit input-output ports (An and Bn) and direction control inputs (DIRn), an output enable input (OE) and dual supply pins (V and V ). Both V and V can be supplied at any CC(A) CC(B) CC(A) CC(B) voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to V and pins Bn are referenced to V . A HIGH on DIRn allows transmission from An to Bn CC(A) CC(B) and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both An and Bn CC(A) CC(B) are in the high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: V : 0.8 V to 3.6 V CC(A) V : 0.8 V to 3.6 V CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E Class 3B exceeds 8000 V CDM JESD22-C101C exceeds 1000 V Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 3.3 V translation) 200 Mbit/s ( 1.1 V to 2.5 V translation) 200 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFFNexperia 74AVC2T245-Q100 2-bit dual supply translating transceiver with configurable voltage translation 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC2T245GU-Q100 -40 C to +125 C XQFN10 plastic, extremely thin quad flat package no leads SOT1160-1 10 terminals body 1.40 x 1.80 x 0.50 mm 4. Marking Table 2. Marking codes Type number Marking code 74AVC2T245GU-Q100 B3 5. Functional diagram 5 4 B1 B2 V V CC(A) CC(B) OE 2 DIR1 DIR2 10 1 A1 A2 8 9 aaa-022963 Fig. 1. Logic symbol OE An DIRn Bn V V CC(A) CC(B) to next transceiver 001aao070 Fig. 2. Logic diagram (one 1-bit transceiver) 74AVC2T245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 1 14 June 2019 2 / 21