NLSX4378A 4-Bit 24 Mb/s Dual-Supply Level Translator The NLSX4378A is a 4bit configurable dualsupply bidirectional auto sensing translator that does not require a directional control pin. The V I/O and V I/O ports are designed to track two different CC L www.onsemi.com power supply rails, V and V respectively. The V and V supply CC L CC L rails are configurable from 1.65 V to 5.5 V. This allows voltage logic signals on the V side to be translated into lower, higher or equal MARKING L DIAGRAM value voltage logic signals on the V side, and viceversa. CC The NLSX4378A translator has opendrain outputs with S4378AB Bump12 integrated 10 k pullup resistors on the I/O lines. The integrated AYWW FC SUFFIX pullup resistors are used to pullup the I/O lines to either V or V . L CC CASE 499AU The NLSX4378A is an excellent match for opendrain applications 2 such as the I C communication bus. A = Assembly Location Y = Year Features WW = Work Week = PbFree Package V can be Less than, Greater than or Equal to V L CC Wide V Operating Range: 1.65 V to 5.5 V CC LOGIC DIAGRAM Wide V Operating Range: 1.65 V to 5.5 V L HighSpeed with 24 Mb/s Guaranteed Date Rate V V GND L CC EN Low BittoBit Skew Enable Input is Overvoltage Tolerant (OVT) to 5.5 V Nonpreferential Powerup Sequencing I/O V 1 I/O V 1 L CC Integrated 10 k Pullup Resistors ESD Protection: >7 kV HBM for all pins I/O V 2 I/O V 2 L CC Small Space Saving Package 2.02 x 1.54 mm Bump12 These Devices are PbFree, Halogen Free/BFR Free and are RoHS Compliant I/O V 3 I/O V 3 L CC Typical Applications 2 I C, SMBus, PMBus I/O V 4 I/O V 4 L CC Low Voltage ASIC Level Translation Mobile Phones, PDAs, Cameras ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. Semiconductor Components Industries, LLC, 2017 1 Publication Order Number: January, 2018 Rev. 0 NLSX4378A/DNLSX4378A V V L CC OneShot OneShot PU1 PU2 Block Block Gate R R Pullup Pullup Bias 10 k 10 k EN EN I/O V I/O V L CC N Figure 1. Block Diagram (1 I/O Line) PIN ASSIGNMENT PIN LOCATION Pins Description Pin Pin Name V V Input Voltage A1 I/O V 1 CC CC L V V Input Voltage A2 I/O V 2 L L L GND Ground A3 I/O V 3 L EN Output Enable A4 I/O VL4 I/O V n V I/O Port, Referenced to V B1 V CC CC CC CC I/O V n V I/O Port, Referenced to V B2 V L L L L B3 EN FUNCTION TABLE B4 GND EN Operating Mode C1 I/O V 1 L HiZ CC C2 I/O V 2 H I/O Buses Connected CC C3 I/O V 3 CC C4 I/O V 4 CC Bump12 (2.02 x 1.54 mm) AB C 1 I/O V 1 V I/O V 1 L CC CC 2 I/O V 2 V I/O V 2 L L CC 3 I/O V 3 EN I/O V 3 L CC 4 I/O V 4 GND I/O V 4 L CC (Bottom View) www.onsemi.com 2