NLSX4401 1-Bit 20 Mb/s Dual-Supply Level Translator The NLSX4401 is a 1bit configurable dualsupply bidirectional auto sensing translator that does not require a directional control pin. The I/O V and I/O V ports are designed to track two different CC L www.onsemi.com power supply rails, V and V respectively. Both the V and V CC L CC L supply rails are configurable from 1.5 V to 5.5 V. This allows voltage logic signals on the V side to be translated into lower, higher or L MARKING equal value voltage logic signals on the V side, and viceversa. CC DIAGRAM The NLSX4401 translator has integrated 10 k pullup resistors UDFN6 on the I/O lines. The integrated pullup resistors are used to pull up M 1.45 x 1.0 the I/O lines to either V or V . The NLSX4401 is an excellent L CC 1 CASE 517AQ 2 match for opendrain applications such as the I C communication bus. Y = Specific Device Code (Rotated 270 clockwise) Features M = Date Code V can be Less than, Greater than or Equal to V L CC Wide V Operating Range: 1.5 V to 5.5 V CC LOGIC DIAGRAM Wide V Operating Range: 1.5 V to 5.5 V L High Speed with 24 Mb/s Guaranteed Date Rate V V GND L CC EN Low BittoBit Skew Enable Input and I/O Pins are Overvoltage Tolerant (OVT) to 5.5 V Nonpreferential Powerup Sequencing I/O V I/O V L CC PowerOff Protection Integrated 10 k Pullup Resistors Small Space Saving Package: 1.45 mm x 1.0 mm UDFN6 Package ORDERING INFORMATION These Devices are PbFree and are RoHS Compliant Device Package Shipping Typical Applications NLSX4401MU1TCG UDFN6 3000 / Tape 2 (PbFree) & Reel I C, SMBus, PMBus For information on tape and reel specifications, Low Voltage ASIC Level Translation including part orientation and tape sizes, please Mobile Phones, PDAs, Cameras refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Important Information ESD Protection for All Pins Human Body Model (HBM) > 5000 V Semiconductor Components Industries, LLC, 2015 1 Publication Order Number: May, 2018 Rev. 3 NLSX4401/D YNLSX4401 Figure 1. Block Diagram (1 I/O Line) 1 6 V V L CC 2 5 I/O V I/O V L CC 4 3 GND EN UDFN6 (Top Through View) Figure 2. Pinout Diagram PIN ASSIGNMENT FUNCTION TABLE Pins Description EN Operating Mode V V Supply Voltage L HiZ CC CC V V Supply Voltage H I/O Buses Connected L L GND Ground EN Output Enable, Referenced to V L I/O V I/O Port, Referenced to V CC CC I/O V I/O Port, Referenced to V L L www.onsemi.com 2