74AVC8T245-Q100 8-bit dual supply translating transceiver with configurable voltage translation 3-state Rev. 3 31 March 2020 Product data sheet 1. General description The 74AVC8T245-Q100 is an 8-bit, dual supply transceiver that enables bidirectional level translation. It features two 8-bit input-output ports (An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (V and V ). Both V and V can be CC(A) CC(B) CC(A) CC(B) supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V and pins Bn are referenced to V . A HIGH on DIR allows transmission CC(A) CC(B) from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both An and Bn CC(A) CC(B) are in the high-impedance OFF-state. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range: V : 0.8 V to 3.6 V V : 0.8 V to 3.6 V CC(A) CC(B) Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 class 3B exceeds 8000 V HBM JESD22-A114E class 3B exceeds 8000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Maximum data rates: 380 Mbit/s ( 1.8 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 3.3 V translation) 260 Mbit/s ( 1.1 V to 2.5 V translation) 210 Mbit/s ( 1.1 V to 1.8 V translation) 150 Mbit/s ( 1.1 V to 1.5 V translation) 100 Mbit/s ( 1.1 V to 1.2 V translation) Suspend mode Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V I circuitry provides partial Power-down mode operation OFF Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder jointsNexperia 74AVC8T245-Q100 8-bit dual supply translating transceiver with configurable voltage translation 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AVC8T245PW-Q100 -40 C to +125 C TSSOP24 plastic thin shrink small outline package SOT355-1 24 leads body width 4.4 mm 74AVC8T245BQ-Q100 -40 C to +125 C DHVQFN24 plastic dual in-line compatible SOT815-1 thermal enhanced very thin quad flat package no leads 24 terminals body 3.5 x 5.5 x 0.85 mm 4. Functional diagram B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 V V CC(A) CC(B) 22 OE 2 DIR 3 4 5 6 7 8 9 10 A1 A2 A3 A4 A5 A6 A7 A8 001aai472 Fig. 1. Logic symbol DIR OE A1 B1 V V CC(A) CC(B) to other seven channels 001aai473 Fig. 2. Logic diagram (one channel) 74AVC8T245 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 3 31 March 2020 2 / 23