74AVCH8T245
8-bit dual supply translating transceiver with configurable
voltage translation; 3-state
Rev. 5 27 December 2012 Product data sheet
1. General description
The 74AVCH8T245 is an 8-bit, dual supply transceiver that enables bidirectional level
translation. It features two 8-bit input-output ports (An and Bn), a direction control input
(DIR), a output enable input (OE) and dual supply pins (V and V ). Both V
CC(A) CC(B) CC(A)
and V can be supplied at any voltage between 0.8 V and 3.6 V making the device
CC(B)
suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V,
2.5 V and 3.3 V). Pins An, OE and DIR are referenced to V and pins Bn are
CC(A)
referenced to V . A HIGH on DIR allows transmission from An to Bn and a LOW on
CC(B)
DIR allows transmission from Bn to An. The output enable input (OE) can be used to
disable the outputs so the buses are effectively isolated.
The device is fully specified for partial power-down applications using I . The I
OFF OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V or V are at
CC(A) CC(B)
GND level, both An and Bn outputs are in the high-impedance OFF-state. The bus-hold
circuitry on the powered-up side always stays active.
The 74AVCH8T245 has active bus hold circuitry which is provided to hold unused or
floating data inputs at a valid logic level. This feature eliminates the need for external
pull-up or pull-down resistors.
2. Features and benefits
Wide supply voltage range:
V : 0.8 V to 3.6 V
CC(A)
V : 0.8 V to 3.6 V
CC(B)
Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Maximum data rates:
380 Mbit/s ( 1.8 V to 3.3 V translation)
260 Mbit/s ( 1.1 V to 3.3 V translation)74AVCH8T245
Nexperia
8-bit dual supply translating transceiver; 3-state
260 Mbit/s ( 1.1 V to 2.5 V translation)
210 Mbit/s ( 1.1 V to 1.8 V translation)
150 Mbit/s ( 1.1 V to 1.5 V translation)
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I circuitry provides partial Power-down mode operation
OFF
Multiple package options
Specified from 40 Cto+85 C and 40 Cto+125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AVCH8T245PW 40 C to +125 C TSSOP24 plastic thin shrink small outline package; 24 leads; SOT355-1
body width 4.4 mm
74AVCH8T245BQ 40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced very SOT815-1
thin quad flat package; no leads; 24 terminals;
body 3.5 5.5 0.85 mm
4. Functional diagram
B1 B2 B3 B4 B5 B6 B7 B8
21 20 19 18 17 16 15 14
V V
CC(A) CC(B)
22
OE
2
DIR
3 45678910
A1 A2 A3 A4 A5 A6 A7 A8 001aai472
Fig 1. Logic symbol
74AVCH8T245 All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet Rev. 5 27 December 2012 2 of 25