74AXP4T245 4-bit dual supply translating transceiver 3-state Rev. 2 6 February 2020 Product data sheet 1. General description The 74AXP4T245 is an 4-bit dual supply translating transceiver with 3-state outputs that enable bidirectional level translation. The device can be used as two 2-bit transceivers or as a 4-bit transceiver. It features four 2-bit input-output ports (nAn and nBn), a direction control input (nDIR), a output enable input (nOE) and dual supply pins (V and V ). Both V and V can CC(A) CC(B) CC(A) CC(B) be supplied at any voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is required and output glitches during power supply transitions are prevented using patented circuitry. As a result glitches will not appear on the outputs for supply transitions during power-up/down between 20 mV/s and 5.5 V/s. Pins nAn, nOE and nDIR are referenced to V and pins nBn are referenced to V . A HIGH CC(A) CC(B) on nDIR allows transmission from nAn to nBn and a LOW on nDIR allows transmission from nBn to nAn. The output enable input (nOE) can be used to disable the outputs so the buses are effectively isolated. The device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both nAn and nBn CC(A) CC(B) are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: V : 0.9 V to 5.5 V CC(A) V : 0.9 V to 5.5 V CC(B) Low input capacitance C = 1.2 pF (typical) I Low output capacitance C = 3.6 pF (typical) O Low dynamic power consumption C = 10 pF (typical) PD Low static power consumption I = 2 A (25 C maximum) CC High noise immunity Complies with JEDEC standard: JESD8-12 (1.1 V to 1.3 V inputs) JESD8-11 (1.4 V to 1.6 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD12-6 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV Latch-up performance exceeds 100 mA per JESD78D Class II Inputs accept voltages up to 5.5 V Low noise overshoot and undershoot < 10% of V CCO I circuitry provides partial power-down mode operation OFF Specified from -40 C to +125 CNexperia 74AXP4T245 4-bit dual supply translating transceiver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AXP4T245PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74AXP4T245BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mm 4. Functional diagram 13 12 11 10 1B1 1B2 2B1 2B2 V V CC(A) CC(B) 1OE 2OE 15 14 1DIR 2DIR 2 3 1A1 1A2 2A1 2A2 001aak280 4 5 6 7 Fig. 1. Logic symbol DIR OE A1 B1 A2 B2 V V CC(A) CC(B) 001aak281 Fig. 2. Logic diagram (one 2-bit transceiver) 74AXP4T245 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 2 6 February 2020 2 / 27