74AXP8T245 8-bit dual supply translating transceiver 3-state Rev. 1 11 February 2020 Product data sheet 1. General description The 74AXP8T245 is an 8-bit dual supply translating transceiver with 3-state outputs that enable bidirectional level translation. It features two data input-output ports (pins An and Bn), a direction control input (DIR), an output enable input (OE) and dual supply pins (V and V ). Both CC(A) CC(B) V and V can be supplied at any voltage between 0.9 V and 5.5 V making the device CC(A) CC(B) suitable for translating between any of the low voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is required and output glitches during power supply transitions are prevented using patented circuitry. As a result glitches will not appear on the outputs for supply transitions during power-up/down between 20 mV/s and 5.5 V/s. Pins An, OE and DIR are referenced to V and pins Bn are referenced to V . A HIGH on CC(A) CC(B) DIR allows transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated. The devices are fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND level, both An and Bn CC(A) CC(B) are in the high-impedance OFF-state. 2. Features and benefits Wide supply voltage range: V : 0.9 V to 5.5 V CC(A) V : 0.9 V to 5.5 V CC(B) Low input capacitance C = 1.5 pF (typical) I Low output capacitance C = 3.8 pF (typical) O Low dynamic power consumption C = 10 pF (typical) PD Low static power consumption I = 2 A (25 C maximum) CC High noise immunity Complies with JEDEC standard: JESD8-12 (1.1 V to 1.3 V inputs) JESD8-11 (1.4 V to 1.6 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) JESD12-6 (4.5 V to 5.5 V) ESD protection: HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2 kV CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1 kV Latch-up performance exceeds 100 mA per JESD78D Class II Inputs accept voltages up to 5.5 V Low noise overshoot and undershoot < 10% of V CCO I circuitry provides partial power-down mode operation OFF Specified from -40 C to +125 CNexperia 74AXP8T245 8-bit dual supply translating transceiver 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AXP8T245PW -40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74AXP8T245BQ -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package no leads 24 terminals body 3.5 x 5.5 x 0.85 mm 4. Functional diagram B1 B2 B3 B4 B5 B6 B7 B8 21 20 19 18 17 16 15 14 V V CC(A) CC(B) 22 OE 2 DIR 3 4 5 6 7 8 9 10 A1 A2 A3 A4 A5 A6 A7 A8 001aai472 Fig. 1. Logic symbol DIR OE A1 B1 V V CC(A) CC(B) to other seven channels 001aai473 Fig. 2. Logic diagram (one channel) 74AXP8T245 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 1 11 February 2020 2 / 27