74CBTLV3861 10-bit bus switch with output enable Rev. 5 16 February 2021 Product data sheet 1. General description The 74CBTLV3861 is a 10-bit bus switch with one output enable (OE) input. When OE is LOW, the switch is closed and port A is connected to the B port. When OE is HIGH, the switch is disabled. To ensure the high-impedance OFF-state during power-up or power-down, OE should be tied to the V through a pull-up resistor. The minimum value of the resistor is determined by the current- CC sinking capability of the driver. Schmitt trigger action at control input makes the circuit tolerant to slower input rise and fall times across the entire V range from 2.3 V to 3.6 V. CC This device is fully specified for partial power-down applications using I . The I circuitry OFF OFF disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Features and benefits Supply voltage range from 2.3 V to 3.6 V High noise immunity Complies with JEDEC standard: JESD8-5 (2.3 V to 2.7 V) JESD8-B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V 5 switch connection between two ports Rail to rail switching on data I/O ports CMOS low power consumption Latch-up performance exceeds 250 mA per JESD78B Class I level A I circuitry provides partial Power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74CBTLV3861PW -40 C to +125 C TSSOP24 plastic thin shrink small outline package 24 leads SOT355-1 body width 4.4 mm 74CBTLV3861BQ -40 C to +125 C DHVQFN24 plastic dual in-line compatible thermal enhanced SOT815-1 very thin quad flat package no leads 24 terminals body 3.5 5.5 0.85 mmNexperia 74CBTLV3861 10-bit bus switch with output enable 4. Functional diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 2 3 4 5 6 7 8 9 10 11 23 OE nB nA 22 21 20 19 18 17 16 15 14 13 OE 001aan143 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 001aan142 Fig. 2. Logic diagram Fig. 1. Logic symbol (one switch) 5. Pinning information 5.1. Pinning 74CBTLV3861 terminal 1 index area A1 2 23 OE A2 3 22 B1 A3 4 21 B2 74CBTLV3861 A4 5 20 B2 A5 6 19 B4 1 24 n.c. V CC A6 7 18 B5 A1 2 23 OE A7 8 17 B6 A2 3 22 B1 A8 9 16 B7 4 21 A3 B2 (1) A9 10 15 B8 GND A4 5 20 B3 A10 11 14 B9 A5 6 19 B4 7 18 A6 B5 001aan146 A7 8 17 B6 A8 9 16 B7 Transparent top view 10 15 A9 B8 (1) This is not a ground pin. There is no electrical or A10 11 14 B9 mechanical requirement to solder the pad. In case GND 12 13 B10 soldered, the solder land should remain floating or 001aan144 connected to GND. Fig. 3. Pin configuration SOT355-1 (TSSOP24) Fig. 4. Pin configuration SOT815-1 (DHVQFN24) 5.2. Pin description Table 2. Pin description Symbol Pin Description n.c. 1 not connected A1, A2, A3, A4, A5, A6, A7, A8, A9, A10 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 data input/output (A port) GND 12 ground (0 V) B1, B2, B3, B4, B5, B6, B7, B8, B9, B10 22, 21, 20, 19, 18, 17, 16, 15, 14, 13 data input/output (B port) OE 23 output enable input (active LOW) V 24 positive supply voltage CC 74CBTLV3861 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 5 16 February 2021 2 / 15 GND 12 1 n.c. B10 13 24 V CC