74HC161D,652 Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT161 Presettable synchronous 4-bit binary counter asynchronous reset December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Presettable synchronous 4-bit binary 74HC/HCT161 counter asynchronous reset FEATURES input (PE) disables the counting action and causes the data at the data inputs (D to D ) to be loaded into the 0 3 Synchronous counting and loading counter on the positive-going edge of the clock (providing Two count enable inputs for n-bit cascading that the set-up and hold time requirements for PE are met). Preset takes place regardless of the levels at count enable Positive-edge triggered clock inputs (CEP and CET). Asynchronous reset A LOW level at the master reset input (MR) sets all four Output capability: standard outputs of the flip-flops (Q to Q ) to LOW level regardless 0 3 I category: MSI CC of the levels at CP, PE, CET and CEP inputs (thus providing an asynchronous clear function). GENERAL DESCRIPTION The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must The 74HC/HCT161 are high-speed Si-gate CMOS devices be HIGH to count. The CET input is fed forward to enable and are pin compatible with low power Schottky TTL the terminal count output (TC). The TC output thus (LSTTL). They are specified in compliance with JEDEC enabled will produce a HIGH output pulse of a duration standard no. 7A. approximately equal to a HIGH level output of Q . This 0 The 74HC/HCT161 are synchronous presettable binary pulse can be used to enable the next cascaded stage. counters which feature an internal look-ahead carry and The maximum clock frequency for the cascaded counters can be used for high-speed counting. is determined by the CP to TC propagation delay and CEP Synchronous operation is provided by having all flip-flops to CP set-up time, according to the following formula: clocked simultaneously on the positive-going edge of the clock (CP). 1 The outputs (Q to Q ) of the counters may be preset to a f = --------------------------------------------------------------------------------------------------- 0 3 max t (CP to TC) + t (CEP to CP) P(max) SU HIGH or LOW level. A LOW level at the parallel enable QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f Notes TYPICAL SYMBOL PARAMETER CONDITIONS UNIT 1. C is used to determine the PD HC HCT dynamic power dissipation (P in W): t / t propagation delay C = 15 pF PHL PLH L D CP to Q V =5 V 19 20 ns 2 n CC P =C V f + D PD CC i CP to TC 21 24 ns 2 (C V f ) L CC o MR to Q 20 25 ns n where: MR to TC 20 26 ns f = input frequency in MHz i CET to TC 10 14 ns f = output frequency in MHz o f maximum clock frequency 44 45 MHz max 2 (C V f ) = sum of L CC o C input capacitance 3.5 3.5 pF I outputs C power dissipation notes 1 and 2 33 35 pF PD C = output load capacitance in L capacitance per package pF V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC December 1990 2