74HC32D-Q100,118 Nexperia

74HC32-Q100 74HCT32-Q100 Quad 2-input OR gate Rev. 4 30 July 2021 Product data sheet 1. General description The 74HC32-Q100 74HCT32-Q100 is a quad 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V . CC This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from -40 C to +85 C and from -40 C to +125 C Wide supply voltage range from 2.0 to 6.0 V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards: JESD8C (2.7 V to 3.6 V) JESD7A (2.0 V to 6.0 V) Input levels: For 74HC32-Q100: CMOS level For 74HCT32-Q100: TTL level Symmetrical output impedance Balanced propagation delays ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC32D-Q100 -40 C to +125 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74HCT32D-Q100 74HC32PW-Q100 -40 C to +125 C TSSOP14 plastic thin shrink small outline package SOT402-1 14 leads body width 4.4 mm 74HCT32PW-Q100 74HC32BQ-Q100 -40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal SOT762-1 enhanced very thin quad flat package no leads 74HCT32BQ-Q100 14 terminals body 2.5 3 0.85 mmNexperia 74HC32-Q100 74HCT32-Q100 Quad 2-input OR gate 4. Functional diagram 1 1 3 2 4 1 6 1 1A 1Y 3 5 2 1B 4 2A 2Y 6 9 5 2B 1 8 10 9 3A 3Y 8 10 3B A 12 12 4A 1 4Y 11 11 Y 13 4B 13 B mna242 mna243 mna241 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one gate) 5. Pinning information 5.1. Pinning terminal 1 index area 1B 2 13 4B 1Y 3 12 4A 1A 1 14 V CC 4 11 2A 32 4Y 2 13 1B 4B 2B 5 (1) 10 3B GND 1Y 3 12 4A 2Y 6 9 3A 2A 4 32 11 4Y 5 10 001aad102 2B 3B Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or 7 8 GND 3Y mechanical requirement to solder the pad. In case 001aad101 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 5.2. Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10,13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) V 14 supply voltage CC 74HC HCT32 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 30 July 2021 2 / 12 GND 7 1 1A 3Y 8 14 V CC