74HC4514DB,112 Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4514 4-to-16 line decoder/demultiplexer with input latches September 1993 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 4-to-16 line decoder/demultiplexer with 74HC/HCT4514 input latches FEATURES The 74HC/HCT4514 are 4-to-16 line decoders/demultiplexers having four binary weighted Non-inverting outputs address inputs (A to A ), with latches, a latch enable input 0 3 Output capability: standard (LE), and an active LOW enable input (E). The 16 outputs (Q to Q ) are mutually exclusive active HIGH. When LE 0 15 I category: MSI CC is HIGH, the selected output is determined by the data on A . When LE goes LOW, the last data present at A are n n GENERAL DESCRIPTION stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents The 74HC/HCT4514 are high-speed Si-gate CMOS of the latch, is HIGH. At E HIGH, all outputs are LOW. The devices and are pin compatible with 4514 of the 4000B enable input (E) does not affect the state of the latch. series. They are specified in compliance with JEDEC standard no. 7A. When the 4514 is used as a demultiplexer, E is the data input and A to A are the address inputs. 0 3 QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay A to Q C = 15 pF V =5 V 23 26 ns PHL PLH n n L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 44 45 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. September 1993 2