74HC670D,652 Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT670 4 x 4 register file 3-state December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 4 x 4 register le 3-state 74HC/HCT670 FEATURES the location of the stored word. When the WE input is LOW, the data is entered into the addressed location. The Simultaneous and independent read and write addressed location remains transparent to the data while operations the WE input is LOW. Data supplied at the inputs will be Expandable to almost any word size and bit length read out in true (non-inverting) form from the 3-state outputs (Q to Q ). D and W inputs are inhibited when Output capability: bus driver 0 3 n n WE is HIGH. I category: MSI CC Direct acquisition of data stored in any of the four registers is made possible by individual read address inputs GENERAL DESCRIPTION (R and R ). The addressed word appears at the four A B The 74HC/HCT670 are high-speed Si-gate CMOS devices outputs when the RE is LOW. Data outputs are in the high and are pin compatible with low power Schottky TTL impedance OFF-state when RE is HIGH. This permits (LSTTL). They are specified in compliance with JEDEC outputs to be tied together to increase the word capacity to standard no. 7A. very large numbers. The 74HC/HCT670 are 16-bit 3-state register files Design of the read enable signals for the stacked devices organized as 4 words of 4 bits each. Separated read and must ensure that there is no overlap in the LOW levels write address inputs (R , R and W ,W ) and enable which would cause more than one output to be active at A B A B inputs (RE and WE) are available, permitting simultaneous the same time. Parallel expansion to generate n-bit words writing into one word location and reading from another is accomplished by driving the enable and address inputs location. The 4-bit word to be stored is presented to four of each device in parallel. data inputs (D to D ). The W and W inputs determine 0 3 A B QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay D to Q C = 15 pF V = 5 V 23 23 ns PHL PLH n n L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 122 124 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC for HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2