INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT93 4-bit binary ripple counter December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 4-bit binary ripple counter 74HC/HCT93 FEATURES divide-by-two section and a the device may be operated in various divide-by-eight section. Each section counting modes. In a 4-bit ripple Various counting modes has a separate clock input (CP and counter the output Q must be 0 0 Asynchronous master reset CP ) to initiate state changes of the connected externally to input CP . 1 1 counter on the HIGH-to-LOW clock The input count pulses are applied to Output capability: standard transition. State changes of the Q clock input CP . Simultaneous n 0 I category: MSI CC outputs do not occur simultaneously frequency divisions of 2, 4, 8 and 16 because of internal ripple delays. are performed at the Q , Q , Q and 0 1 2 GENERAL DESCRIPTION Therefore, decoded output signals Q outputs as shown in the function 3 are subject to decoding spikes and table. As a 3-bit ripple counter the The 74HC/HCT93 are high-speed should not be used for clocks or input count pulses are applied to input Si-gate CMOS devices and are pin strobes. CP . 1 compatible with low power Schottky Simultaneous frequency divisions of TTL (LSTTL). They are specified in A gated AND asynchronous master 2, 4 and 8 are available at the Q , Q 1 2 compliance with JEDEC standard reset (MR and MR ) is provided 1 2 and Q outputs. Independent use of 3 no. 7A. which overrides both clocks and the first flip-flop is available if the reset resets (clears) all flip-flops. The 74HC/HCT93 are 4-bit binary function coincides with reset of the ripple counters. The devices consist Since the output from the 3-bit ripple-through counter. of four master-slave flip-flops divide-by-two section is not internally internally connected to provide a connected to the succeeding stages, QUICK REFERENCE DATA GND = 0 V T =25C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay CP to Q 12 15 ns PHL PLH 0 0 C = 15 pF V =5 V L CC f maximum clock frequency 100 77 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 22 22 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz f = output frequency in MHz i o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF V = supply voltage in V L CC 2. For HC the condition is V = GND to V for HCT the condition is V = GND to V - 1.5 V I CC I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2