74HCT00D Nexperia

74HC00 74HCT00 Quad 2-input NAND gate Rev. 6 14 December 2011 Product data sheet 1. General description The 74HC00 74HCT00 are high-speed Si-gate CMOS devices that comply with JEDEC standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL). The 74HC00 74HCT00 provides a quad 2-input NAND function. 2. Features and benefits Input levels: For 74HC00: CMOS level For 74HCT00: TTL level ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC00N 40 C to +125 C DIP14 plastic dual in-line package 14 leads (300 mil) SOT27-1 74HCT00N 74HC00D 40 C to +125 C SO14 plastic small outline package 14 leads body width SOT108-1 3.9 mm 74HCT00D 74HC00DB 40 C to +125 C SSOP14 plastic shrink small outline package 14 leads body SOT337-1 width 5.3 mm 74HCT00DB 74HC00PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74HCT00PW 74HC00BQ 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package no leads 14 terminals 74HCT00BQ body 2.5 3 0.85 mm74HC00 74HCT00 NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram 1 & 3 1 1A 2 1Y 3 2 1B 4 4 2A & 6 2Y 6 5 5 2B 9 9 3A 3Y 8 & 8 10 3B 10 A 12 4A 12 4Y 11 Y 13 4B & 11 13 B mna212 mna246 mna211 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning 74HC00 74HCT00 74HC00 terminal 1 74HCT00 index area 2 13 1B 4B 1A 1 14 V CC 1Y 3 12 4A 1B 2 13 4B 2A 4 11 4Y 1Y 3 12 4A 2A 4 11 4Y 2B 5 (1) 10 3B GND 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A GND 7 8 3Y 001aal324 Transparent top view 001aal323 (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14 Fig 5. Pin configuration DHVQFN14 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 74HC HCT00 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 14 December 2011 2 of 16 GND 7 1 1A 8 14 3Y V CC