74HCT166D Nexperia

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT166 8-bit parallel-in/serial-out shift register December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 8-bit parallel-in/serial-out shift register 74HC/HCT166 FEATURES an active LOW parallel enable (PE) input. When PE is LOW one set-up time prior to the LOW-to-HIGH clock Synchronous parallel-to-serial applications transition, parallel data is entered into the register. When Synchronous serial data input for easy expansion PE is HIGH, data is entered into the internal bit position Q 0 from serial data input (D ), and the remaining bits are s Clock enable for do nothing mode shifted one place to the right (Q Q Q , etc.) with 0 1 2 Asynchronous master reset each positive-going clock transition. For asynchronous parallel data load see 165 This feature allows parallel-to-serial converter expansion by tying the Q output to the D input of the succeeding Output capability: standard 7 s stage. I category: MSI CC The clock input is a gated-OR structure which allows one input to be used as an active LOW clock enable (CE) input. GENERAL DESCRIPTION The pin assignment for the CP and CE inputs is arbitrary The 74HC/HCT166 are high-speed Si-gate CMOS devices and can be reversed for layout convenience. The and are pin compatible with low power Schottky TTL LOW-to-HIGH transition of input CE should only take place (LSTTL). They are specified in compliance with JEDEC while CP is HIGH for predictable operation. A LOW on the standard no. 7A. master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all bit positions The 74HC/HCT166 are 8-bit shift registers which have a to a LOW state. fully synchronous serial or parallel data entry selected by QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5 V PHL PLH L CC CP to Q 15 20 ns 7 MR to Q 14 19 ns 7 f maximum clock frequency 63 50 MHz max C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 41 41 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2