INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4027B flip-flops Dual JK flip-flop January 1995 Product specication File under Integrated Circuits, IC04Philips Semiconductors Product specication HEF4027B Dual JK ip-op ip-ops DESCRIPTION FUNCTION TABLES The HEF4027B is a dual JK flip-flop which is INPUTS OUTPUTS edge-triggered and features independent set direct S C CP J K O O D D (S ), clear direct (C ), clock (CP) inputs and outputs D D (O,O). Data is accepted when CP is LOW, and transferred HL X X X H L to the output on the positive-going edge of the clock. The LH X X X L H active HIGH asynchronous clear-direct (C ) and set-direct D HH X X X H H (S ) are independent and override the J, K, and CP inputs. D The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. INPUTS OUTPUTS S C CP J K O O D D n + 1 n + 1 L L L L no change LL H L H L LL L H L H LL H H O O n n Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition O = state after clock positive transition n + 1 PINNING J,K synchronous inputs CP clock input (L to H edge-triggered) S asynchronous set-direct input (active HIGH) D C asynchronous clear-direct input (active HIGH) D O true output O complement output Fig.1 Functional diagram. HEF4027BP(N): 16-lead DIL plastic (SOT38-1) HEF4027BD(F): 16-lead DIL ceramic (cerdip) (SOT74) HEF4027BT(D): 16-lead SO plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, I LIMITS category FLIP-FLOPS DD See Family Specifications Fig.2 Pinning diagram. January 1995 2