74LV4094D,118 Nexperia

74LV4094 8-stage shift-and-store bus register Rev. 8 18 March 2021 Product data sheet 1. General description The 74LV4094 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess V . CC 2. Features and benefits Optimized for low voltage applications over a wide supply voltage range from 1.0 V to 3.6 V Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and T = 25 C OH CC amb CMOS low power dissipation Direct interface with TTL levels Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Complies with JEDEC standards JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 C 3. Applications Serial-to-parallel data conversion Remote control holding registerNexperia 74LV4094 8-stage shift-and-store bus register 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV4094D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LV4094DB -40 C to +125 C SSOP16 plastic shrink small outline package 16 leads SOT338-1 body width 5.3 mm 74LV4094PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 5. Functional diagram 3 1 1 C2 15 EN3 CP STR QS1 9 SRG8 3 QS2 10 C1/ QP0 4 2 4 1D 2D 3 5 QP1 5 6 QP2 6 2 D 7 QP3 7 14 QP4 14 13 QP5 13 12 QP6 12 11 9 QP7 11 OE 10 15 001aaf111 001aaf112 Fig. 1. Functional diagram Fig. 2. Logic symbol D 2 8-STAGE SHIFT QS2 10 CP REGISTER 3 QS1 9 STR 8-BIT STORAGE 1 REGISTER OE 15 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 5 6 7 14 13 12 11 001aaf119 Fig. 3. Logic diagram 74LV4094 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 18 March 2021 2 / 17