74LV541PW,112 NXP

74LV541 Octal buffer/line driver 3-state Rev. 03 14 April 2009 Product data sheet 1. General description The 74LV541 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC541 and 74HCT541. The 74LV541 has octal non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high-impedance OFF-state. 2. Features n Optimized for low voltage applications: 1.0 V to 3.6 V n Accepts TTL input levels between V = 2.7 V and V = 3.6 V CC CC n Typical output ground bounce < 0.8 V at V = 3.3 V and T = 25 C CC amb n Typical HIGH-level output voltage (V ) undershoot: > 2 V at V = 3.3 V and OH CC T =25 C amb n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Non-inverting outputs n Multiple package options n Specied from - 40 Cto+85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LV541N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74LV541D - 40 C to +125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74LV541DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74LV541PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm74LV541 NXP Semiconductors Octal buffer/line driver 3-state 4. Functional diagram A0 Y0 2 18 A1 Y1 3 17 A2 Y2 4 16 A3 Y3 5 15 Y4 A4 6 14 1 & EN 19 Y5 A5 7 13 18 2 17 3 Y6 A6 8 12 16 4 15 5 Y7 A7 11 9 6 14 7 13 8 12 OE1 1 9 11 OE2 19 mna180 mna900 Fig 1. Logic symbol Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning 74LV541 74LV541 1 20 1 20 OE1 V OE1 V CC CC 2 19 2 19 A0 OE2 A0 OE2 3 18 3 18 A1 Y0 A1 Y0 4 17 4 17 A2 Y1 A2 Y1 5 16 5 16 A3 Y2 A3 Y2 6 15 6 15 A4 Y3 A4 Y3 7 14 7 14 A5 Y4 A5 Y4 8 13 8 13 A6 Y5 A6 Y5 9 12 9 12 A7 Y6 A7 Y6 10 11 10 11 GND Y7 GND Y7 001aaj964 001aaj965 Fig 3. Pin conguration DIP20, SO20 Fig 4. Pin conguration, (T)SSOP20 74LV541 3 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 03 14 April 2009 2 of 15