74LVC139D,118 Nexperia

74LVC139 Dual 2-to-4 line decoder/demultiplexer Rev. 6 24 September 2021 Product data sheet 1. General description The 74LVC139 decodes two binary weighted address inputs (nA0, nA1) to four mutually exclusive outputs (nY0 to nY3). Each decoder features an enable input (nE). When nE is HIGH all outputs are forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power dissipation Direct interface with TTL levels Demultiplexing capability Two independent 2-to-4 decoders Multifunction capability Mutually exclusive outputs Output drive capability 50 transmission lines at 125 C Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC139D -40 C to +125 C SO16 plastic small outline package 16 leads SOT109-1 body width 3.9 mm 74LVC139PW -40 C to +125 C TSSOP16 plastic thin shrink small outline package 16 leads SOT403-1 body width 4.4 mm 74LVC139BQ -40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced SOT763-1 very thin quad flat package no leads 16 terminals body 2.5 3.5 0.85 mmNexperia 74LVC139 Dual 2-to-4 line decoder/demultiplexer 4. Functional diagram 4 4 DX X/Y 0 0 1 2 2 0 5 1 5 0 1 1 G 3 3 3 6 6 1E 1 2 2 2 4 1 1 1Y0 7 EN 7 3 3 2 5 1A0 1Y1 3 6 1A1 1Y2 12 12 DX X/Y 0 0 7 14 14 1Y3 0 11 1 11 0 12 1 1 G 13 13 2Y0 3 10 10 1 2 2 2 14 11 15 15 2A0 2Y1 9 EN 9 13 10 3 3 2A1 2Y2 9 2Y3 (a) (b) mna781 2E (a) demultiplexer 15 mna779 (b) decoder Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1Y0 4 2 1A0 1Y1 5 DECODER 3 1A1 1Y2 6 1Y3 7 1 1E 2Y0 12 2A0 14 2Y1 11 DECODER 13 2A1 2Y2 10 2Y3 9 2E 15 mna780 Fig. 3. Functional diagram 74LVC139 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 6 24 September 2021 2 / 14